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TIMESCALEMOD verilator error when attempting to add a new black box in chisel

I'm trying to add a new blackboxed verilog module to the chipyard hardware generation framework and simulate it with verilator .

My changes pass chipyard's scala compilation phase in which the chisel hardware specification is compiled into verilog. However, it appears during the "verilation" process in which that verilog is translated into a C++ executable, I'm encountering an error:

%Error-TIMESCALEMOD: [filename].v:238066:15: Timescale missing on this
module as other modules have it (IEEE 1800-2017 3.14.2.2)
chipyard/sims/verilator/generated-src/. . ./ClockDividerN.sv:8:8: ...
Location of module with timescale
    8 | module ClockDividerN #(parameter DIV = 1)(output logic clk_out = 1'b0, input clk_in);
      |        ^~~~~~~~~~~~~ %Error: Exiting due to 1 error(s)

Searching around, the "timescale" this is referring to appears to be a configuration option for verilator simulations to do with how much time (usually in picoseconds) advances during one step of the simulation.

What's strange is the error claims that this module "ClockDividerN" (also a blackboxed verilog module included in the chipyard generator's vsrc directory) has a timescale, but the verilog source for ClockDividerN does not contain anything that appears to be a timescale.

Likewise, adding a timescale directive to the verilog source I'm trying to integrate produces the same error message. There are some verilator command-line options to do with timescales, but they're difficult to add in in the chipyard framework (it uses a pretty opaque makefile to run verilator).

Any help?

Update: the documentation for handling a TIMESCALEMOD error recommends using the "--timescale" command-line argument, but it turns out chipyard's Makefile for verilator simulations already uses that argument!

When adding your blackbox resources, something has gone wrong. Make sure the addResource path is correct. The TIMESCALEMOD error has nothing to do with this, but the blackbox path being included incorrectly causes that error to go off.

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