I'm trying to add a new blackboxed verilog module to the chipyard hardware generation framework and simulate it with verilator. My changes pass chipy ...

I'm designing a cpu core using Xilinx axi ram IP. To speed up the simulation, I want to transplant the simulation environment to verilator. However, t ...

I am trying to add an accelerator to the rocket chip framework through the MMIO peripheral. I went through the GCD example and was able to build the b ...

I have a system which I want to trace with Verilator, but using a VCD trace file is highly resource-demanding (hundreds of gigabytes) and time consumi ...

When compiling RTL from multiple sources it is normal to compile them into separate SystemVerilog libraries. Doing this means they cannot interfere wi ...

I'm trying to familiarize myself with (sub)modules in verilog and I am running into errors I cannot explain. I have these two files: top.v: serial ...

I've implemented a (working) ripple-carry adder using generation to create 16 different full_adder instances (the full_adder works as intended): No ...

I'm following this tutorial. On page 24 I don't get the Makefile the tutorial talks about. When I run ./thruwire it says: bash: ./thruwire: Invalid ar ...

I am trying to compile and link the runtime support code for Verilator (veripool.org). It builds fine, but for some reason there are a couple of metho ...

I'm going through the infamous nand2tetris course and decided to construct a computer in verilog using only primitive nand gates and modules I build o ...

I am using Verilog to set up FPGA so that it blinks an LED once per second. And this is one way to do it: Now I wrote this makefile: First two m ...

I am reading a wonderful Verilator tutorial and in these slides (page 25) author uses a library call: I know that tfp is a pointer to a Verilator l ...

I'm using Verilator to simulate a circuit from a very simple program that just repeatedly sets the clock line high, and then low, until some output co ...

I try to make a .dll from the Verialtor source code, since they've implemented this possibility. They use a common handler typedef void* svScope to i ...

I tried with this example, but nothing happens: For example, if I change the CMAKE_ANDROID_ARCH_ABI to anything else, nothing happens. It is like C ...

To test my Verilog design I'm using two differents simulators : Icarus and Verilator. It's work, but there are some variations between them. For exam ...

I'm following the README here to get set up: https://github.com/chipsalliance/rocket-chip. When I run make -j6 run in my $ROCKETCHIP/emulator director ...

I want to cast logic packed array into longint unsigned in systemverilog and then I can export it using DPI-C to C++ unsigned long. The simulator I am ...

So I have the following register defined in my verilog My goal is from my verilator c++ code to read each of the 16 values stored in it. I have fo ...

This is a slightly modified version of the HelloWorld.scala example from https://github.com/freechipsproject/chisel3/wiki/Frequently-Asked-Questions ...