Sequential element is unused and will be removed from module in vivado

Question

I got the warning "[Synth 8-6014] Unused sequential element MVM_RST_reg was removed. " I am a little bit confused, because the signal is connected and used

The definition:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.math_real.all;
use work.parameters.all;

entity MVM is
  port (
    EN:         IN std_logic;
    DIN:        IN  signed(DATA_WIDTH_IN-1 downto 0);
    WEIGHT:     IN  signed(DATA_WIDTH_IN -1 downto 0);
    CLK:        IN  std_logic;
    RST:        IN  std_logic;
    MVM_RESULT: OUT signed(DATA_WIDTH_IN-1 downto 0):= (OTHERS => '0')
  );
end entity MVM;
  
architecture base of MVM is

begin
  process(CLK)
  variable acc_value : signed(DATA_WIDTH_IN-1 downto 0):= (OTHERS => '0');
  begin
   IF rising_edge(CLK) then
      IF RST='1' THEN
        acc_value := (OTHERS => '0'); -- reset accumulated value to 0
      ELSIF EN='1' THEN 
        acc_value := resize((acc_value + WEIGHT* DIN), DATA_WIDTH_IN); 
        MVM_RESULT <= acc_value;
      END IF;
    END IF;
  END process;

end base;

My component

    component MVM is
      port (
        EN:                             in          std_logic;
        DIN:                            IN          signed(DATA_WIDTH_IN-1 downto 0);
        WEIGHT:                         IN          signed(DATA_WIDTH_IN-1 downto 0);
        CLK:                            IN          std_logic;
        RST:                            IN          std_logic;
        MVM_RESULT:                     OUT         signed(DATA_WIDTH_IN-1 downto 0)
      );

The signal

signal MVM_RST:                     std_logic;

My instantiation

MVM_UNITS: MVM
                port MAP(
                    EN                  => MVM_En,
                    DIN                 => DIN_Array(i) ,
                    Weight              => WEIGHT_Array(i),
                    CLK                 => CLK,
                    RST                 => MVM_RST,
                    MVM_RESULT          => MVM_RESULT_ARRAY(i)
                );

the usage of the Reset

state_machine:  process(Clk) is
        begin
           if rising_edge(Clk) then
               IF RST='1' then
                    MVM_RST             <= '1';         
               Else   
                     MVM_RST             <= '0'; 

In detail the warning is reffering to the line RST=> MVM_RST of the instantiation

Answer 1

MVM_RST_reg is removed, because you reset acc_value instead of MVM_RESULT. acc_value is a variable and not a signal. This means, you will only get flipflops for acc_value, if there is a situation were you read acc_value before you assign a value to it. If RST=1, then you assign a value to acc_value but you do not read its value. So no flipflop is needed. If RST=0 and EN=1, then you first assign a value and then read it. So again, no flipflop is needed. As there is no flipflop for acc_value build in, you cannot reset any flipflops by MVM_RST. So the MVM_RST_reg is removed.