Initialize a constant array of std_logic_vector from binary file in VHDL

Question

I have packaged an IP and in its top module I have a constant array of std_logic_vector for some purpose. If I need to use only a single instance of this IP in the design, I can edit this constant array for my needs and voila, however if I need multiple instances of this IP (this constant array should be different for each of those instances) I have to find another way to do that because when I change the constant array for one of these IP instances, others are also changed because they are using the same VHDL source file obviously. How can I overcome this issue? One way I think about is introducing an input port for the top wrapper of my IP so that it takes this array from outside, and when I instantiate it in the design top level I can create multiple constant arrays and connect them to the IP instances accordingly. Do you have any other suggestions to accomplish this task?

Here is my code with X = 4, Y = 32 (they are much more larger in real case). Up to this point I was using python to find my comments -- DO NOT CHANGE BETWEEN COMMENTS -- and -- COMMENT END HERE -- , and change what is inside according to another text file automatically.

type myarray_t is array (X - 1 downto 0) of std_logic_vector(Y - 1 downto 0);

-- DO NOT CHANGE BETWEEN COMMENTS --
constant myarray : myarray_t := (x"01234567",
                                 x"89abcdef",
                                 x"01234567",
                                 x"89abcdef");
-- COMMENT END HERE --

Answer 1

Pack your constants into a VHDL package and use them from there. Create several files, which all contain the same VHDL-package. Then you can have in each of these files a different version of your constants. You include the constants by "use work.package_name.all" in your design. At compile time you compile your design and 1 of the packages in a single library, but create as much different compiled libraries as you have different versions of the package file. When you instantiate your design, you then must define from which library the instance has to be taken. You can define this by a embedded configuration in the architecture declaration area of your toplevel like:

for instance1: use entity library1.your_design;
for instance2: use entity library2.your_design;

Or you can define it at the instantiation in your toplevel design:

instance1: entity library1.your_design port map ...
instance2: entity library2.your_design port map ...