Verilog testbench

Question

I wanted to write my own testbench, but it doesn't give me an output. I tried everything I could, but it didn't helped. Can anyone give me a hand in this?

module direct(clk, reset, x, y);
input clk, reset;
input signed [7:0]x;
output signed [23:0]y;
reg signed [23:0]y;
reg signed [15:0]a[0:8]; //coeff
reg signed [7:0]rej[0:8]; //reg
reg signed [23:0]acc; 
reg [4:0]count; //

always@(posedge clk)
begin: states
   parameter s0=0, s1=1, s2=2, s3=3;
    reg[1:0] state;
    integer i;
    if(reset == 0) begin
        state <= s0;
    end
    else begin

    case(state)
        s0: begin
            state <= s1;
            acc <= 0;
            a[0] <= 16'd887; 
            a[1] <= 16'd553;
            a[2] <= -16'd2563;
            a[3] <= -16'd8745;
            a[4] <= 16'd19757;
            a[5] <= -16'd8745;
            a[6] <= -16'd2563;
            a[7] <= 16'd553;
            a[8] <= 16'd887;
            for (i=0; i<9; i=i+1) 
                rej[i] <= 0;
            end

        s1: begin
            state <= s2;
            count <= 0;
            acc <= 0;
            rej[0]<= x; 
            for (i = 1; i <9; i=i+1)
                rej[i] <= rej[i-1];
            end

        s2: begin
            if(count ==9) 
                state <= s3;
            else
                begin
                    state <= s2;
                    count <= count + 1'd1;
                    acc <= acc + rej[count]*a[count];
                end
            end

        s3: begin
            state <= s1;
            y <= acc;
            end
            default:state <=s0;
        endcase
    end
end
endmodule

My own testbench: (if anyone could point what i did wrong)

`timescale 1 ns / 100 ps
module direct_test();
reg clk, reset;
reg [7:0]x;
wire [23:0]y;

    direct U1(
            .clk(clk),
            .reset(reset), 
            .x(x),
            .y(y)
            );
    always
    #10 clk = ~clk;
    initial 
    begin
    clk = 1'b0;
    #5 reset <= 1'b0;
    x <= 1'd1;
    #10 reset <= 1'b1;
end
endmodule

Answer 1

There is a compile error in the direct module. Change:

    for (i = 1; i <9; i=i+1) rejestry

to:

    for (i = 1; i <9; i=i+1)

The always block in the direct_test module prevents the simulation from completing. Add a $finish to the initial block:

    initial 
    begin
    clk = 1'b0;
    #5 reset <= 1'b0;
    x <= 1'd1;
    #10 reset <= 1'b1;
    #5000 $finish;
end

With these changes, I see y change in waveforms from X to 'h377, 'h5a0, etc.