Bidirectional port in verilog testbench

Question

How do we assign an input to a bidirectional port in Verilog testbench ?

I have a design and an associated testbench. The relevant part of design is as follows:

module i2cModule (
input   wire        mod_en , 
input   wire        rec_ack ,
input   wire        burst_write , burst_read ,
input   wire        [7 : 0] data_tx ,   
output  wire        [7 : 0] data_rx ,   
output  wire        ack ,
inout   wire    scl ,
inout   wire    sda 
) ;

// Some code here

send_command :
    begin   
        case (bit_counter)          // Parallel to serial convertor
            7   : sda_reg = ( !scl) ? data_tx[7] : sda_reg ;
            6   : sda_reg = ( !scl) ? data_tx[6] : sda_reg ;
            5   : sda_reg = ( !scl) ? data_tx[5] : sda_reg ;
            4   : sda_reg = ( !scl) ? data_tx[4] : sda_reg ;
            3   : sda_reg = ( !scl) ? data_tx[3] : sda_reg ;
            2   : sda_reg = ( !scl) ? data_tx[2] : sda_reg ;
            1   : sda_reg = ( !scl) ? data_tx[1] : sda_reg ;
            0   : sda_reg = ( !scl) ? data_tx[0] : sda_reg ;
        endcase 
        start_bit_counter = (scl && !bit_counter) ? 1'b0 : start_bit_counter ;
        i2c_next = (!start_bit_counter) ? wait_ack : send_command ;
    end

    wait_ack :
    begin
        ack_reg = ( scl) ? sda : ack_reg ;
        start_bit_counter = ( scl) ? 1'b1 : 1'b0 ;
        i2c_next = (scl && !ack_reg) ? (data_tx[7] ? rx_mode : tx_mode ) : wait_ack ;
    end

// Some code here

Testbench is as follows:

module i2c_test;

// Inputs
reg mod_en;
reg rec_ack;
reg burst_write;
reg burst_read;
reg [7:0] data_tx;

// Outputs
wire [7:0] data_rx;
wire ack;

// Bidirs
wire scl;
wire sda;

// Some stimulus here ; all stimulus in initial block

    mod_en = 1 ;
    data_tx = 8'b10101010 ;             // Write mode
    repeat (8) @ (posedge scl) ;    // Wait 8 clocks for command to be sent
    sda = 1'b0 ;                                            // slave ack
    @ (posedge scl) ;

The design synthesizes successfully for target device. However, in testbench, when I try to drive sda , it gives an error. Also, if change sda to reg, then also it says that outputs cannot be reg type.

How do I drive sda in testbench?

Answer 1

If you need to drive a bidir signal from another module or a test bench, you can do like this:

wire [7:0] input_value;
wire [7:0] bidir_signal;
reg [7:0] output_value;
reg output_value_valid;

mymodule myinstance (
  ...
  ...
  .bidir_signal(bidir_signal),
  ...
  ...
);

assign input_value = bidir_signal;
assign bidir_signal = (output_value_valid==1'b1)? output_value : 8'hZZ;

initial begin
  output_value_valid = 0;
  // use bidir_signal as input here so you can read its current value
  //
  $display ("Current value: %x\n", input_value);
  #100;
  // now we switch to output signal: we write value 10101010 in it
  output_value_valid = 1;
  output_value = 8'hAA;
  #100;
  $finish;
end