Verilog: compare wire values in testbench

Question

In testbench I was trying to do a very simple comparison, namely data_a !== 32'h14 , which surprisingly resulted in true , yet in the simulation I saw clearly that data_a is exactly 32'h14 .

If I compare it using != then it's false as expected.

The reason why I don't want to use != is because it may result in X which will act as false in my test case. I have already had falsely passing tests as a result of this.

My only guess why data_a !== 32'h14 may be true is that data_a consists of St0 St0 St0 ... and 32'h14 of 0 0 0 ... as you can see from the picture:

My understanding was that 0 is an alias of St0 , so not sure whether that may be the reason.

Full code of the testbench is below:

module test_registers(clk);
    input clk;

    reg error = 0;
    reg write = 0;
    reg [4:0] addr_a = 0, addr_b = 0, addr_in = 0;
    reg [31:0] data_in = 0;
    wire [31:0] data_a, data_b;

    register_file MUT(data_a, data_b, addr_a, addr_b, addr_in, data_in, write, clk);

    initial begin
       $readmemh("tests/registers/reg.dat", MUT.registers);

       addr_a = 1;
       addr_b = 2;
       if (data_a !== 32'h14 || data_b !== 32'h40) begin
           $display("Fetch 1 failed");
           error = 1;
       end

    end
endmodule

UPD. The answer was a race condition (read more about those in the verilog tutorial , Chapter 3) There was literally no time spent between setting addr_a and reading the result ( data_a ) - the module register_file updated it at the same point in time ( 0 ), but later than the read. A solution might be to add a delay (eg #1 ) between set and read, so that all the actions scheduled for the time slot 0 are guaranteed to have executed.

Answer 1

Most likely this is a race condition. data_a is probably still 32'bx at time 0 when the If statement execute. Put a $display in front of it. Wires take some delta cycles to propagate value changes. Strength is used only when there are multiple drivers on a wire to resolve the value to a 0,1, X or Z.

Answer 2

Verilog initializes all wires to 'x'.

An initial block executes at time 0, before any real simulation is done. So values of data_a and data_b are 'x' at the time of your 'if' statement. 'x' is not === equal to h14 or h40; So, your condition is rightfully evaluated to true. As a result, your 'fetch' is supposed to fail.

the === operator returns true if you compare absolutely identical variables where 'x' is compared to 'x' and returns true.

'x' === 'x' ==> true
'x' === '1' ==> false