How to write string values in Verilog testbench?

Question

I am trying to write a Verilog test-bench where I have to write output of some registers. I want to write L instead of 0 , and H instead of 1 eg '100101' as g 'HLLHLH' . I know about writing binary, hex or decimal value, but I am not sure whether it can be done in Verilog or not?

Answer 1

Assuming you're not using SystemVerilog, you could write a task, eg:

task LHwrite (input integer bin, input integer length);
  integer i;
  for (i=length-1; i>=0; i=i-1)
    $write("%s", "L"-(bin[i]*8'h4));
endtask 

bin is the value you want to display (up to 32 bits); length is the number of bits you want to display. The task iterates over the input:

for (i=length-1; i>=0; i=i-1)

and then uses the $write system task (which is like $display but without a newline) to display the string you want. This is calculated based on the knowledge that the ASCII code for 'H' is 8'h48 and for 'L' is 8'h4C .

https://www.edaplayground.com/x/4Ewk

module M;

  task LHwrite (input integer bin, input integer length);
    integer i;
    for (i=length-1; i>=0; i=i-1)
      $write("%s", "L"-(bin[i]*8'h4));
  endtask 

  initial
    begin : test
      reg [5:0] bin = 6'b100101;
      LHwrite(bin, 6);
      $write("\n");
    end

endmodule

Answer 2

System verilog testbench is a programming language. You can do normal programming things in it. However, in this case you would need to create your resulting string bit by bit like in the following example:

program a;
  bit [3:0] data  = 4'b1100;
  initial begin
    string out;
    $display("%b ==> ", data);
    for (int i = 0; i < $bits(data); i++) begin
      if ((data & ($bits(data)) == 0)
        out = {"L", out};
      else 
        out = {"H", out};
      data >>= 1;
    end
    $display(" ==> %s", out);
  end
endprogram

result:

1100 ==> 
  ==> HHLL