How to write a verilog testbench to loop through 4 inputs?

Question

I have to create the verilog code and testbench for this schematic.

I have the design for it here.

module prob1(input wire a,b,c,d, output wire out);
    assign out = (a||d)&&(!d&&b&&c);
endmodule

Here is what I have for the testbench so far.

module prob1_tb();
    reg a,b,c,d;
    wire out;

    prob1 prob1_test(a,b,c,d, out);

    initial begin
        for(i=0; i=16; i=i+1)
            <loop code here>
        end
    end
endmodule

Now I guess the part I am having issue with is how can I convert that number into those 4 inputs that are being used in the schematic. Or is there a better way to go about doing this?

Answer 1

Here is a simple way using the concatenation operator:

module prob1(input wire a,b,c,d, output wire out);
    assign out = (a||d)&&(!d&&b&&c);
endmodule

module prob1_tb();
    reg a,b,c,d;
    wire out;

    prob1 prob1_test(a,b,c,d, out);

    initial begin
        $monitor(a,b,c,d,out);
        for (int i=0; i<16; i=i+1) begin
            {a,b,c,d} = i;
            #1;
        end
    end
endmodule

Output:

00000
00010
00100
00110
01000
01010
01100
01110
10000
10010
10100
10110
11000
11010
11101
11110

Yes, there are better ways to verify logic. The first thing to do is to introduce random values (refer to the $urandom functions in the IEEE Std 1800-2009). Of course, you also need to perform checks of your output using a model, which in your case is trivial.

Depending on how much time (and training) you have, you could adopt a standard flow, such as the Universal Verification Methodology (UVM). People build careers around verification.