伊势模拟VHDL

Question

I would like to ask the following. I am working on an FPGA Tetris design. My code language is VHDL in ISE Environment in windows 7.

While I progress my work I ofter check my work with isim simulation. As the design is getting big isim stops working and closes. Basically the module causing this crash is a big fsm. When I comment some states of the fsm ISIM is working fine again.

It doesn't matter which states I will comment. I can check the fsm working in parts. But I can not test it as a whole. Is it possible that this is not code error and it is just ISIM?

Thanks

Answer 1

How to split a complex FSM into parts?
Here are some example lines to illustrate a simple call/return handshaking protocol between a main FSM and two function FSMs

process(Clock)
begin
    if (Reset = '1') then
        MainFSM_State       <= ST_IDLE;
        Func1FSM_State  <= ST_IDLE;
        Func2FSM_State  <= ST_IDLE;
    else
        MainFSM_State       <= MainFSM_NextState;
        Func1FSM_State  <= Func1FSM_NextState;
        Func2FSM_State  <= Func2FSM_NextState;
    end if;
end process;

process(MainFSM_State, Input, ...,
                Func1FSM_Output, Func1FSM_Return,
                Func2FSM_Output, Func2FSM_Return)
begin
    Func1FSM_Call           <= '0';
    Func2FSM_Call           <= '0';

    MainFSM_Output      <= x"00";

    case MainFSM_State is
        when ST_IDLE =>
            if (Input = '1') then
                Func1FSM_Call               <= '1';
                MainFSM_NextState       <= ST_FUNC1_EXECUTING;
            end if;

        when ST_FUNC1_EXECUTING =>
            MainFSM_Output              <= Func1FSM_Output;

            if (Func1FSM_Return = '1') then
                Func2FSM_Call               <= '1';
            end if;

       ....
    end case;
end process;

Some general hints for your design (based on the code snippet)

Using big FSMs is also very fault-prone. So one goal of writing big FSMs should be readability, so you can find errors more easily.

• Don't use std_logic_arith, std_logic_unsigned while numeric_std is used. Use only numeric_std, that's adequate.

• wait until is not a synthesizeable statement. Use:

   if rising_edge(clk) then ... end if; 

• Are your external inputs like reset_switch synchronized and debounced? A signal name like reset_switch implies that this signal is raw ;)

• You can improve the readability of if..elsif..else..end if; statements by using case statements (see line 230)

• You use masses of binary assignments like t_left_most <= "010111"; --23 t_left_most <= "010111"; --23 . Maybe it's better to declare t_left_most with another type (eg a constrained natural), so you can use integer literals in your FSM. For exporting these signals to other modules the signal is converted back to std_logic_vector. -> improved readability

• Some times it's good to introduce constants eg

   constant C_TOP_MOST : NATURAL := 0; 

• I would advice you to extract your counter memReadAddress from your FSM. Big FSMs should only generate flow-control signals, FSMs should not contain any data-flow logic (counters, multiplexers, ...). So extract the counter to a separate process and add control signals to your big FSM.

   when T_block_1 => ReadAddressCounter_en <= '1'; 

  Personally, I use prefixes like _rst, _en, _us, _inc, _dec for the counter control signals. _us stands for unsigned, because the my counters are unsigned counters and the value is converted to std_logic if needed.

  Counter example with FSM 'remote control' signals:

   process(Clock) begin if rising_edge(Clock) then if ((Reset or MemAddressCounter_rst) = '1') then MemAddressCounter_us <= (others => '0'); else if (MemAddressCounter_load = '1') then MemAddressCounter_us <= to_unsigned(5, MemAddressCounter_us'length); elsif (MemAddressCounter_inc = '1') then MemAddressCounter_us <= MemAddressCounter_us + 1; end if; end if; end if; end process; MemAddress <= std_logic_vector(MemAddressCounter_us); 

• line 286 should not be synthesizable (I think Xilinx XST is not smart enough and if so, it's not predictable what XST would produce ...)

   dataIn<=dataOut(39 downto conv_integer(T_left_most+1))&T_square&T_square&T_square&dataOut(conv_integer(T_right_most-1) downto 0); 

So how can you fix the last point in the list of my hints?

1. simple way: use a 40:1 multiplexer
2. more advanced way: try to use mask and bit-shift operations
3. use another data structure, which is more suitable for hardware :)

If you want a more detailed discussion on this points, please leave a comment and I will try to extend my answer.

Extended answer - bit operation solution

So lets summarize line 286:

dataIn <= dataOut(39 downto conv_integer(T_left_most+1)) &
          T_square & T_square & T_square &
          dataOut(conv_integer(T_right_most-1) downto 0);

Your result consists of 3 parts:

• dataout sliced from MSB downto dynamic marker
• 3 bits
• dataout sliced from dynamic marker downto 0

This bit insertion can also be done by a bitwise set/clear operation:

• set: result <= input or set_mask;
• clear: result <= input and not clear_mask;

This can be combined to a bit override operation:

• override: result <= (input and not override_mask) or override_value;
• secure override result <= (input and not override_mask) or (override_value and override_mask);

The latter must be used if you can not assume that override_value has only bits set within the range of override_mask.

The next step is to move T_square to the right position. Shifting bits in a fast way can be done by a barrel-shifter or a multiplier (DSP block). Because your vector has 40 bits, a barrel-shifter is faster then a DSP block.

A barrel shifter of 64 bits has a 6 bit shift_value input. Each bit of the input specifies if the value should be shifted by a power of two.

entity arith_BarrelShifter is
  generic (
    BITS            : POSITIVE      := 32
  );
  port (
    Input           : in    STD_LOGIC_VECTOR(BITS - 1 downto 0);
    ShiftAmount     : in    STD_LOGIC_VECTOR(log2ceilnz(BITS) - 1 downto 0);
    Output          : out   STD_LOGIC_VECTOR(BITS - 1 downto 0)
  );
end;

architecture rtl of arith_BarrelShifter is
  constant STAGES       : POSITIVE      := log2ceilnz(BITS);

  subtype   T_INTERMEDIATE_RESULT is STD_LOGIC_VECTOR(BITS - 1 downto 0);
  type  T_INTERMEDIATE_VECTOR is array (NATURAL range <>) of T_INTERMEDIATE_RESULT;

  signal IntermediateResults    : T_INTERMEDIATE_VECTOR(STAGES downto 0);

begin
  IntermediateResults(0)    <= Input;
  Output                    <= IntermediateResults(STAGES);

  for i in 0 to STAGES - 1 generate
    process(IntermediateResults(i), ShiftRotate, LeftRight, ArithmeticLogic)
    begin
      if (ShiftAmount(i) = '0') then
        IntermediateResults(i + 1) <= IntermediateResults(i);
      else
        IntermediateResults(i + 1) <= IntermediateResults(i)((BITS - i**2 - 1) downto 0) & ((i**2 - 1) downto 0 => '0');                                                        -- SLA, SLL
      end if;
    end process;
  end generate;
end;

So now we can combine all steps:

override_value <= (39 downto 3 => '0') & (2 downto 0 => T_square);
override_mask  <= (39 downto 3 => '0') & (2 downto 0 => '1');

shift_value : entity PoC.arith_BarrelShifter
  generic map (
    BITS        => 40
  )
  port map (
    Input       => override_value,
    ShiftAmount => T_left_most,
    Output      => shifted_value
  );

shift_mask : entity PoC.arith_BarrelShifter
  generic map (
    BITS        => 40
  )
  port map (
    Input       => override_mask,
    ShiftAmount => T_left_most,
    Output      => shifted_mask
  );

--           clear bits from source   / set bits from value
dataIn <= (dataOut and not shifted_mask) or shifted_value;

I hope I made no mistakes :)