模块内的模糊内部的参数

Question

I have read about parameters and how to redefine them at module instantiation but what if i have a parameter inside a module inside a module say that i have a small module called gen

module gen(input,output);
parameter n=2;
parameter m=10;
//do something
endmodule

that module is instantiated in another module called top

module top(inputs,output);
gen gen1(inputs,output);
//do something
endmodule;   

and i am trying to make a testbench on the big module where i need to redefine the two parameter n and m

module tb;
reg input;
wire output;
top top1(input,output)
endmodule;

how can i write that in verilog?

Answer 1

One solution is to redefine the parameters at each level:

module gen(input,output);
parameter n=2;
parameter m=10;
//do something
endmodule


module top(inputs,output);
parameter n=2;
parameter m=10;
gen #(.n(n), .m(m)) gen1(inputs,output);
//do something
endmodule;   

module tb;
reg input;
wire output;
top #(.n(n), .m(m)) top1(input,output)
endmodule;

Another solution is to keep your current module definition and use defparam in your testbench to hierarchically override the value of parameters:

module tb;
reg input;
wire output;
defparam top1.gen1.m = 4;
defparam top1.gen1.n = 5;
top top1(input,output)
endmodule;