如何在Verilog中的if语句中实例化模块？

Question

if (btn[0] == 1)
    begin
        operaciones op(A,B,numop,C);
        display disp(C,led);
    end

I need to instantiate it inside this if, how can i do that?

Answer 1

Before you go and use a generate statement for this (which allows module instantiation inside an if statement), you need to consider what you are saying. From what it appears you are trying to do in your code snippet, when button 0 is pressed, you want to do some operation and display the result on the LEDs. However, you are treating modules like function calls when they are something very different.

Module instantiations are declarations that the module hardware exists within its parent module. So, when I have something like this:

module top;

  module_name instances_name( ... );

endmodule

I declare that a module_name (all the hardware of module_name ) exists within top (which probably has more hardware). Think of modules as ICs and the parent module as a breadboard, instantiating that module is like putting that IC down on the breadboard with the port connections being your wires to each pin of that IC. All the ICs necesary to do anything that design does exist on in the circuit somewhere; they dont appear and disappear depending on what the user inputs.

Now think back to what you wanted to say: you are saying, when buttton 0 is pressed, put this IC on the breadboard. If not pressed, take it away. As ICs dont appear and disappear from a circuit board, this doesnt make sense. So you need to treat module instantiations the same way you'd treat ICs if you were building the design on a breadboard; you can declare there is hardware to preform this operation (put down and wire up the IC), and when botton 0 is pressed, route the output from that hardware to the LEDs (using another IC or small circuit to do the routing; think mux).

Answer 2

只需添加@Unn所说的内容，您真正需要实例化模块，然后在if语句中打开（或关闭）模块的启用信号。