Makefile-命令中的命令？

Question

I have an embarrassingly simple makefile question but I can't google it due to lack of knowledge - I don't know the words for things I don't know.

Basically, I want to run the makefile in the current directory, look into the ./SRC directory for source files and when everything is finished, move the object files into the ./OBJ directory.

Makefile:

move_obj: 
    mv -f -t ./OBJ_DIR ./$(OBJ_FILES)

file.o: other_file.h 
    $(CC) $(CFLAGS) $(CPPFLAGS) -c file.c
    move_obj

I want to call "move_obj" after compiling the source files but since I don't know what

result: dependency
    evaluation

actually represents (and all makefile introduction guides I've found state "This is what a makefile looks like, off you go then"), I don't know why this isn't working. I assume I need some evaluate command or need to define a function or...?

Thanks for any help in advance.

Answer 1

You can do this by creating another rule for example move , like below

all: $(EXECUTABLE) move

$(EXECUTABLE):  $(OBJECTFILES)
            $(CC) -o $@ $<
$(OBJECTFILES): $(SOURCEFILES)
            $(CC) $(CFLAGS) -c -o $@ -I $(INCLUDE_PATH) $<

# Move the .o to Object directory #
move:           
            $(MV) $(OBJECTFILES) $(OBJECT_PATH)

---

But by doing the above, you will defeat the purpose of the Makefile .
Since your rule is dependent on .o , Make will look for .o in current directory and not find it (because you've moved it) and thus rebuild.

To avoid this, you should output it to ./obj directory and use it from there.
Something like

gcc -g -Wall -o obj/foo.o  -c src/foo.c  -I ./include
gcc -g -Wall -o obj/main.o -c src/main.c -I ./include
gcc -o  exe  obj/foo.o obj/main.o -lanylibrary

Below is the makefile doing the same.

C_FLAGS := -g -Wall -Wextra
CC := gcc
RM := rm
LINKFLAGS := -lanylibrary

.PHONY: $(TARGET) clean

VPATH:= ./src/ ./obj/ ./include/

# Path for .c , .h and .o Files 
SRC_PATH := ./src/
OBJ_PATH := ./obj/
INC_PATH := -I ./include

# Executable Name 
TARGET := exe

# Files to compile
OBJ1 := foo.o \
        main.o

OBJ := $(patsubst %,$(OBJ_PATH)%,$(OBJ1))

# Build .o first
$(OBJ_PATH)%.o: $(SRC_PATH)%.c
                @echo [CC] $<
                @$(CC) $(C_FLAGS) -o $@ -c $< $(INC_PATH)                  

# Build final Binary
$(TARGET):      $(OBJ)
                @echo [INFO] Creating Binary Executable [$(TARGET)]
                @$(CC) -o $@ $^ $(LINKFLAGS)

# Clean all the object files and the binary
clean:   
                @echo "[Cleaning]"
                @$(RM) -rfv $(OBJ_PATH)*
                @$(RM) -rfv $(TARGET)

---

Refer to this answer for a better understanding

EDIT :
You can also output your executable to directory, add the following changes to your Makefile .
Ensure that the bin directory is created beforehand, and not deleted by clean .

# Path for .c , .h and .o Files, and ./bin directory
BIN_PATH := ./bin

# Executable Name 
TARGET := $(BIN_PATH)/exe

# Clean all the object files and the binary
clean:   
                @echo "[Cleaning]"
                @$(RM) -rfv $(OBJ_PATH)*
                @$(RM) -fv $(TARGET)

Answer 2

If you want to build a target( move_obj ) after another(file.o), add the move_obj to the dependency list of file.o so that the commands under the move_obj will be executed.

So your Makefile should be:

file.o: other_file.h move_obj
    $(CC) $(CFLAGS) $(CPPFLAGS) -c file.c

move_obj: 
    mv -f -t ./OBJ_DIR ./$(OBJ_FILES)

As Colonel Thirty Two mentioned in the comment section, instead of compiling and then move, you can build the object files in the required directory

file.o: other_file.h
    $(CC) $(CFLAGS) $(CPPFLAGS) -c file.c -o ./$(OBJ_FILES)/$@

Answer 3

This is flawed in various ways.

1. result normally is an actual file that should be present after the recipe is executed. If the file is already there and is not older than any of its dependencies, make does nothing. So instead of creating a file somewhere and then moving it around with another rule, make sure the rule creates it where it should FINALLY be. Otherwise make can never check whether it has to rebuild it (and always will). In this case, use the -o flag of the compiler to directly create it where it should be (eg -o $(OBJ_DIR)/file.o )

2. dependency should list ALL files that are needed to build the result , so make really rebuilds it if ANY of these files changed. In your case, at least file.c is missing from the dependency list

3. In order to place files in a directory, you should make sure it exists. you could do it like this:

    $(OBJ_DIR): mkdir -p $(OBJ_DIR) $(OBJ_DIR)/file.o: $(OBJ_DIR) file.c other_file.h $(CC) $(CFLAGS) $(CPPFLAGS) -c file.c -o $(OBJ_DIR)/file.o 

4. Your move_obj recipe, although not suitable in this case, would be a PHONY target, meaning it does not create a file. If you need such rules, mark them accordingly by mentioning them as dependency of the special target .PHONY :

    .PHONY: move_obj 

   The reason for this is that you could (by accident) have a file named move_obj in your working directory. In that case, make would decide there's nothing to do for move_obj, and this is not what you want. Marking it as phony tells make that this rule does not create its target and the recipe must be executed no matter what.

All in all, your question comes down to misunderstanding a Makefile as kind of a script. It is not. It's a declarative file that tells make what has to be done in order to build files (your evaluation block) and when this needs to be done (your dependency block). It's better not to try to misuse a Makefile as a script.