SystemC中与verilog wire等效的功能是什么？

Question

I'm converting some verilog code to SC. Here is a case made me confused: In verilog, a continuous assignment such as:

wire a;
assign a =1;

Where a will get 1 immediately after the assignment. If we write it in SC:

sc_signal<bool> a;
a.write(1);

The current value of a will not be 1. How to resolve this problem? Like the following?

bool a;
a = 1;

Answer 1

In Verilog, you are not guaranteed to read the updated value of a continuous assignment if you are changing the RHS and reading the LHS in two different processes synchronized to the same time. You need to use a non-blocking assignment to avoid a race condition.

In SystemC, the write() method is similar to a non-blocking assignment. The difference is that you are required to use the write() method in SystemC. So .you should only be writing to signals as the output of a thread/process. If you need to read the signal within the process, then you need to use a variable local to the thread.