[英]Verilog slight drops in signal caused by clock change?
I have a circuit designed to debounce a switch.我有一个设计用于去抖动开关的电路。 It samples the signal every 1 ms and counts for 8ms in a shift register.它每 1 ms 采样一次信号,并在移位寄存器中计数 8 ms。 When the register has counted 8 1ms ticks of a high signal ,we assume the signal is clean and output sig_clean goes high.当寄存器计数高信号的 8 个 1ms 滴答时,我们假设信号是干净的并且输出 sig_clean 变高。 For some reason, every tick of the 1KHz clock (the 1 ms clock), my clean signal drops to 0 and then goes right back up at the next tick of the onboard clock.出于某种原因,1KHz 时钟(1 ms 时钟)的每一个滴答声,我的干净信号都会下降到 0,然后在板载时钟的下一个滴答声中又恢复原状。 Any idea why this is happening?知道为什么会这样吗?
`timescale 1ns / 1ps
module debounce(
input Clk100MHz, reset_n, Clk1KHzEn, sig,
output reg sig_clean);
reg [7:0] sigconfirm;
initial sigconfirm = 8'b0000_0000;
initial sig_clean = 0;
always@(posedge Clk100MHz)
begin
if(~reset_n)
sig_clean <= 0;
else
if(Clk1KHzEn == 1)
begin
if(sig == 1)
begin
sigconfirm[7] <= 1;
sigconfirm = sigconfirm >> 1;
end
else
begin
sigconfirm[7] <= 0;
sigconfirm = sigconfirm >> 1;
end
end
end
always@(posedge Clk100MHz)
begin
if(sigconfirm == 8'b1111_1111)
sig_clean <= 1;
else
sig_clean <= 0;
end
endmodule
The testbench:测试台:
`timescale 1ns / 1ps
module lab_7_top_tb();模块 lab_7_top_tb();
reg Clk100MHz, BTNC, BTNU;
wire CA, CB, CC, CD, CE, CF, CG, DP;
wire [7:0] AN;
lab_7_top labtop(
.Clk100MHz(Clk100MHz),
.BTNC(BTNC),
.BTNU(BTNU),
.CA(CA),
.CB(CB),
.CC(CC),
.CD(CD),
.CE(CE),
.CF(CF),
.CG(CG),
.DP(DP),
.AN(AN)
);
initial Clk100MHz = 0;
always #5 Clk100MHz = ~Clk100MHz;
initial begin
BTNC = 1'b1; BTNU = 1'b0;
#100;
BTNC = 1'b0;
#1000;
press_BTNU;
#1000;
press_BTNU;
#1000;
$finish;
end
task press_BTNU;
begin
$display("%d Start of press button task", $time);
BTNU = 0;
#1000;
BTNU = 1;
#1500;
BTNU = 0;
#1200;
BTNU = 1;
#1800;
BTNU = 0;
#1100;
BTNU = 1;
#15000;
BTNU = 0;
#1800;
BTNU = 1;
#1600;
BTNU = 0;
#1400;
BTNU = 1;
#1100;
BTNU = 0;
#15000;
$display("%d End of press button task", $time);
end
endtask
endmodule结束模块
Turns out the issue was 2 fixes: I fixed the blocking assignment like Serge suggested, and I swapped the order that sigconfirm shifted and assigned the bit, to get:原来问题是 2 个修复:我像 Serge 建议的那样修复了阻塞分配,我交换了 sigconfirm 移位和分配位的顺序,以获得:
sigconfirm <= sigconfirm >> 1;
sigconfirm[7] <= 1'b1;
and now life is good!现在生活很好!
You put your reset
of sig_clean
in the wrong always
block.您将sig_clean
的reset
放在错误的always
块中。 Should be应该
always @(posedge Clk100MHz)
if (!reset_n)
sig_clean <= 0;
else if(sigconfirm == 8'b1111_1111)
sig_clean <= 1;
else
sig_clean <= 0;
endmodule
声明:本站的技术帖子网页,遵循CC BY-SA 4.0协议,如果您需要转载,请注明本站网址或者原文地址。任何问题请咨询:yoyou2525@163.com.