如何在Alteras Quartus-II FPGA IDE中实例化宏功能

Question

I use the web (ie free) edition of Alteras FPGA IDE. According to the documentation, it hosts at least some of the Altera megafunctions. A response to an earlier tech forum enquiry indicates that it does.

I've tried to use them, but without success. When I 'create' an instance using the Altera Megafunction guide, all that comes out is something like a 'pure virtual function' for a COM object, ie. a function prototype / data structure. I can't seem to be able to actually instantiate a working function, and can't find any actual working Verilog code. It would be great if someone could point me to some information that might help.

Specifically, if using megafunctions, is code created in an accessible form such as Verilog, or is the functionality in the form of a netlist or some other non-user-accessible format?

Answer 1

Megafunction is softcore and hardcore IP, and It is not accessible as verilog code, at some level u can see. but can't able to decode full IP core RTL. Yes!, it is some other non-user-accessible format. click here for megafunction import procedure.

Answer 2

本文档可能会为您提供帮助： Altera Doc，它是关于RAM宏功能的，但是有一些有关如何实例化宏功能的信息（即第24/64页）