VHDL IF语句不起作用

Question

I've got a problem with VHDL's if syntax. The code looks as follows:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Shifting_zero is
    port (clk : in STD_LOGIC;
            zeros : buffer STD_LOGIC_VECTOR (3 downto 0));
end Shifting_zero;

architecture Behavioral of Shifting_zero is
begin

process
    begin
        if (clk'event and clk='1') then
            if (zeros='0111') then 
                zeros <= '1011';
            elsif (zeros='1011') then
                zeros <= '1101';
            elsif (zeros-'1101') then
                zeros <= '1110';
            else
                zeros <= '0111';
            end if;
        end if;
end process;

end Behavioral;

I receive the following errors:

Line 15. parse error, unexpected PROCESS

Line 18. parse error, unexpected TICK

Line 20. parse error, unexpected TICK

Line 23. parse error, unexpected TICK

Line 26. parse error, unexpected END, expecting SEMICOLON

Line 12. No sensitivity list and no wait in the process (warning)

I'm new to VHDL and pretty confused by those errors.

Answer 1

OK, I found it.

I had to use " instead of ' in signals.