如何在Verilog模式Emacs中删除尾随空格

Question

I'm trying to delete trailing whitespaces in Verilog Mode. I have customized Verilog mode with the menu : "Verilog --> Customize Verilog Mode...".

Trailing whitespaces are not removing when editing or saving a Verilog file. I've tried somme commands 'add hook' but still no success. What am I missing ?

That's my .emacs (Emacs 24.3.1) :

`(custom-set-variables
;; custom-set-variables was added by Custom.
;; If you edit it by hand, you could mess it up, so be careful.
;; Your init file should contain only one such instance.
;; If there is more than one, they won't work right.
'(cua-mode t nil (cua-base))
'(global-whitespace-mode t)
'(indent-tabs-mode nil)
'(show-paren-mode t)
'(verilog-align-ifelse t)
'(verilog-auto-delete-trailing-whitespace t)
'(verilog-auto-endcomments nil)
'(verilog-auto-hook (quote (delete-trailing-whitespace)))
'(verilog-auto-indent-on-newline t)
'(verilog-auto-lineup (quote declarations))
'(verilog-auto-newline nil)
'(verilog-indent-level 2)
'(verilog-indent-level-behavioral 2)
'(verilog-indent-level-declaration 2)
'(verilog-indent-level-directive 2)
'(verilog-indent-level-module 2)
'(verilog-indent-lists nil)
'(verilog-tab-always-indent t))
(custom-set-faces
;; custom-set-faces was added by Custom.
;; If you edit it by hand, you could mess it up, so be careful.
;; Your init file should contain only one such instance.
;; If there is more than one, they won't work right.
)`

Answer 1

In general, not just for Verilog, I use the below clean up before save:

;; Before save
;; (add-hook 'before-save-hook 'delete-trailing-whitespace)
(add-hook 'before-save-hook 'whitespace-cleanup)

You can try enabling 'delete-trailing-whitespace only, if the 'whitespace-cleanup does too much.