在Emacs Verilog模式中对齐代码？

Question

I'm used to writing code in VHDL in emacs, which has the nice beautify functionality that will align signal assignments. Is there something similar with the Verilog Mode?

Convert this:

r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

To This:

r_Tx_Done     <= 1'b1;
r_Clock_Count <= 0;
if (r_Done == 1'b1)
  begin
    r_SM_Main   <= s_CLEANUP;
    o_Tx_Active <= 1'b0;
  end

Verilog mode does a good job keeping if else begin end aligned, but it doesn't align assignments like I want. Note that inside the if statement doesn't align to <= outside the if statement. Essentially I want each begin/end block treated separately.

Answer 1

I use verilog mode, and I have found this works by default.

1. Type Cx h to highlight the entire buffer.
2. Then TAB to get it to beautify everything. Much easier and less tedious!

Answer 2

Based on this answer you can try to customize align-rules-list .

Something like this should help:

(eval-after-load "align"
  '(add-to-list 'align-rules-list
                '(verilog-assignment
                  (regexp . "\\(\\s-*\\)<=")
                  (mode   . '(verilog-mode))
                  (repeat . nil))))

Now Mx align should apply the new alignment rule.

Answer 3

In Verilog mode for GNU Emacs 24.3.1 you can place the cursor on the non-blocking assignment operator "<=" in any of the assignment operations. For instance, in the top portion of the code:

r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;

place the cursor on either of the assignment operators and type Cc = . The code will now become

r_Tx_Done     <= 1'b1;
r_Clock_Count <= 0;

This operation will only be performed in that section of code. This operation will not jump into any other statements: if-else, case, always, etc. In order to perform the same operation in another statement you would have to go inside that statement click on an assignment operator and type Cc = again.