在Emacs Verilog模式下的if语句后插入“begin”

Question

I have been using Emacs to create and modify Verilog codes for some time now. However, in Verilog mode, I am facing a small issue when I try to insert an "if" statement using the emacs command:

Cc Ct ?

The following is an example of how the statement is created in the above scenario:

if (a<b) begin
// the rest of the code

However I need emacs to insert the "begin" in the next line as shown below:

if (a<b)
begin
//rest of the code

After digging through the Verilog customization options available, I found one option named Verilog Indent Begin After If which I think is supposed to produce the above effect. However toggling this option did not give my any visible changes.

Any help would be greatly appreciated.

Answer 1

Looking at the code you will see that the function:

(define-skeleton verilog-sk-if
  "Insert a skeleton if statement."
  > "if (" '(verilog-sk-prompt-condition) & ")" " begin" \n
  > _ \n
  > (- verilog-indent-level-behavioral) "end " \n )

actually defines a skeleton. Just copy paste and add another line-break:

(define-skeleton my-verilog-sk-if
  "Insert a skeleton if statement."
  > "if (" '(verilog-sk-prompt-condition) & ")" \n " begin" \n
  > _ \n
  > (- verilog-indent-level-behavioral) "end " \n )

now we just need to hook our function over the old one in verilog-mode:

(add-hook 'verilog-mode-hook
          '(lambda ()
             ;; this is quite the hack because we don't respect
             ;; the usual prefix of verilog-mode but sufficient for us
             (define-key verilog-mode-map "\C-c\C-t?"
                         'my-verilog-sk-if)))