在vhdl / verilog中如何合理化建模的抽象级别

Question

I'm a beginner in VHDL and in some books they say behavioural model has highest abstraction and dataflow model has middle level abstraction and structural model has low level abstraction .

How they are justified? And on which situations which modelling should be used?

I assume when to use behavioural which is a sequential model as follows:

         if(all_doors_locked) then 
         ignition_start = 1;

But the other two models being concurrent,I couldn't able to find any difference between them,then

how their abstraction level is varied? And when they can be used like in the example above?

Answer 1

Behavioural Model:

always @ (*)
begin
  if(all_doors_locked) 
     ignition_start = 1'b1;
  else
     ignition_start = 1'b0;
end

Data-flow Model:

always @ (*)
begin
     ignition_start = all_doors_locked;
end

Structural Model:

buf  U1(ignition_start,all_doors_locked);

Looking at " Behavioural " design, may classify it as a design approach where modules are modeled at a high level of abstraction where the designer defines the desired behaviour of the module and the synthesis tools decompose that behaviour to either RTL or Structural models.

Less abstract is "RTL" or Register Transfer Logic modeling. This is where many practitioners say that " data-flow " begins. Where we actually write Hardware,

assign Y = A & B; // AND operation     

Least abstract is " Structural " modeling where the design is stated almost exclusively as component instantiations with connecting registers and wires.

Answer 2

Structural gate level is what every digital circuit should be finally implemented to. That is the hardware implementation of every digital circuit. But, in a large design, it is really hard for a human to take a very large netlist and get a grasp on it and understand what it is doing.

Behavioral model is what we humans, easily understand because many details are abstracted away. However, it is not always possible to convert it to gates easily.

Dataflow (or RTL) is somewhere int he middle: It is still not too hard to understand it, and it can be converted in an automated and systematic way into gates. That is why many designers use this level of abstraction for real world designs.

One analogy to this in software is the high-level description of a software application (Behavioral model). It's source code, eg C++, resembles dataflow level, and it compiled machine code resembles the structural gate level netlist.