Verilog Testbench的输出均为x或z

Question

I do not understand verilog terribly well so this may be some simple issue with the way I have things set up, but I cannot seem to identify why my simulation waveform yields either x or z for my testbench outputs. Here is the module I am simulating:

module addsub_4bit (Sum, Ovflw, A, B, sub);
input [3:0] A, B;
input sub;
output [3:0] Sum;
output Ovflw;

wire cin, c0, c1, c2, c3;

assign B[3:0] = (sub) ? (~B + 1) : B;
assign cin = 0;
assign Ovflw = (c3 ^ c2);

full_adder_1bit fa0 (.sum(Sum[0]), .cout(c0), .a(A[0]), .b(B[0]), .cin(cin));
full_adder_1bit fa1 (.sum(Sum[1]), .cout(c1), .a(A[1]), .b(B[1]), .cin(c0));
full_adder_1bit fa2 (.sum(Sum[2]), .cout(c2), .a(A[2]), .b(B[2]), .cin(c1));
full_adder_1bit fa3 (.sum(Sum[3]), .cout(c3), .a(A[3]), .b(B[3]), .cin(c2));

endmodule

and my testbench:

module addsub_4bit_tb();
reg [7:0] stim;
reg sub;
wire [3:0] Sum;
wire Ovflw;
integer i;

addsub_4bit DUT(.Sum(Sum), .A(stim[3:0]), .B(stim[7:4]), .Ovflw(Ovfw), 
.sub(sub));

initial begin

stim = 0;
sub = 0;
#100;
for(i=0; i<16; i=i+1) begin
stim = stim + 1;
#100;
end 

stim = 0;
sub = 1;
#100;
for(i=0; i<16; i=i+1) begin
stim = stim + 1;
#100;
end

end

initial $monitor("A= %d\tB= %d\nAdd/Sub= %b\nSum= %d\tOvflw= 
%b",stim[3:0],stim[7:4],sub,Sum,Ovflw);

endmodule

My output gives that Sum = x and Ovflw = z. The single bit full adder module that I use to compose my 4 bit adder works fine and was tested. I appreciate any feedback.

Answer 1

For overflow bit,there is a typo in testbench :

.Ovflw(Ovfw),

For Sum vector getting x issue, the input B has multiple drivers , one in testbench and another in RTL itself:

.B(stim[7:4]) // TB driver
assign B[3:0] = (sub) ? (~B + 1) : B; // RTL driver

So, to avoid this, take some intermediate wire in RTL and assign value of B or ~B to it. Here I have used wire X to drive single bit adders.

wire [3:0] X;
//...
assign X[3:0] = (sub) ? (~B + 1) : B;
//...
full_adder_1bit fa0 (.sum(Sum[0]), .cout(c0), .a(A[0]), .b(X[0]), .cin(cin));
//... 

Refer to this link for more information on multiple drivers. If you are using SystemVerilog, then you can use logic datatype to avoid multiple driver issue.