SystemVerilog值不在typedef枚举内

Question

I can't figure out where I am going wrong. I have a command structure (actually around 100 commands) defined in a similar manner as follows.

    typedef enum bit [15:0] { 
     CMD_1A           = 16'h1000,
     CMD_1B           = 16'h1100,
     CMD_1C           = 16'h1110,
     CMD_2A           = 16'h2000,
     CMD_2B           = 16'h2100,
     CMD_2C           = 16'h2200,
     CMD_2D           = 16'h2300,
     CMD_3A           = 16'h3000,
     CMD_4A           = 16'h4000,
     CMD_4B           = 16'h4010
      } command_type_e;

     rand command_type_e cmd_type;

Around the first # (1, 2, 3 or 4) I have a class which breaks out format. These commands have common parts while other command sections are unique. This is easy enough to control since all the valid values are defined in this typedef.

After checking valid commands defined in the list I want to check is all the undefined values so I can see how my command controller handles them and if these invalid messages get discarded correctly.

I tried to create an invalid group and constrain it to be not inside the valid types but this doesn't work.

    rand bit [15:0] inv_cmd_type;
    constraint not_in_range {!(inv_cmd_type inside {command_type_e});}

I tried a couple other ways without much success. I can put in specific values but that is a mess especially since that list would have to be tracked every time a new command is created.

Thoughts on how to define all the items not in that list?

Thanks!

Answer 1

You can create a list of all literals inside the enum using the pattern described in section 6.19.5.7 Using enumerated type methods of the 2012 LRM. Adapted to your case (and fixed formatting):

command_type_e cmd = cmd.first;
command_type_e all_cmds[$];
forever begin
  all_cmds.push_back(cmd);
  if (cmd == cmd.last())
    break;
  cmd = cmd.next();
end

Based on this list, it's trivial to create a constraint.