将多个值与 SystemVerilog 中的变量进行比较

Question

I have logic to compare a variable with multiple values.我有逻辑将变量与多个值进行比较。 For example:例如：

logic [3:0] a;
always_comb begin
    flag = (a == 'd13) || (a == 'd2) || (a=='d1); //can this be simplified?
end

Is there a easy way to write this statement?有没有简单的方法来写这个语句？

Answer 1

This is more concise using the inside operator:使用inside运算符更简洁：

always_comb begin
    flag = (a inside {1, 2, 13});
end

This is more scalable as well, allowing you to easily add or remove values from the set.这也更具可扩展性，允许您轻松地从集合中添加或删除值。

The syntax also supports ranges of values:该语法还支持值范围：

    flag = (a inside {[1:2], 13});

Refer to IEEE Std 1800-2017, section 11.4.13 Set membership operator.请参阅 IEEE Std 1800-2017，第 11.4.13 节设置成员资格运算符。

Since the values in the set are all constants, it should be synthesizable (but YMMV).由于集合中的值都是常数，它应该是可综合的（但 YMMV）。