[英]Variable assignment in SystemVerilog generate statement
I have created a simple module that I replicate several times using the Verilog generate statement. 我创建了一个简单的模块,可以使用Verilog generate语句复制多次。 However, it seems that the generate statement somehow effects variable assignment in the module.
但是,似乎generate语句以某种方式影响模块中的变量分配。 Here's the code:
这是代码:
module test();
timeunit 10ns;
timeprecision 1ns;
wire[3:0] out;
reg[3:0] values[0:4] = {5, 6, 7, 8, 9};
logic clk;
generate
genvar i;
for (i=0; i < 5; i++) begin: M1
MUT mut(
.out,
.in(values[i]),
.clk
);
end
endgenerate
initial begin
#1 clk = 0;
$monitor("%b %b %b %b %b\n", M1[0].mut.out, M1[1].mut.out, M1[2].mut.out, M1[3].mut.out, M1[4].mut.out);
#10 $stop;
end
always #1 clk++;
endmodule
module MUT(output [3:0] out, input [3:0] in, input clk);
reg[3:0] my_reg[0:7];
assign out = my_reg[7];
always @(posedge clk) begin
my_reg[7] <= in; //5
end
endmodule
The expected output of this test program would be 0101 0110 0111 1000 1001
, however the output I get is xxxx xxxx xxxx xxxx
. 该测试程序的预期输出为
0101 0110 0111 1000 1001
,但是我得到的输出为xxxx xxxx xxxx xxxx
。 It seems that the values in the values
variable in the test
module are not getting assigned to the out
variable in the MUT
module. 似乎
test
模块中的values
变量中的values
未分配给MUT
模块中的out
变量。 However, when I replace my_reg[7] <= in;
但是,当我替换
my_reg[7] <= in;
with say, my_reg[7] <= 5;
用
my_reg[7] <= 5;
, the code works as expected. ,代码按预期工作。 The code also works when I assign directly to
out
(after declaring it as register) ie out <= in;
当我直接分配给
out
(在将其声明为寄存器之后),即out <= in;
时,该代码也适用out <= in;
. 。 There's no problem if I replicate the
MUT
modules 'manually' without using any generate statements. 如果我不使用任何generate语句而“手动”复制
MUT
模块,就没有问题。
You are not connecting the outputs to separate wires. 您没有将输出连接到单独的电线。 So they are implicitly tied together(like how it did for clock) resulting multiple drivers for a bit.
因此它们隐式地绑在一起(就像时钟一样),从而导致了多个驱动程序。
Just add 只需添加
wire[3:0] out[0:4];
generate
genvar i;
for (i=0; i < 5; i++) begin: M1
MUT mut(
.out(out[i]), // Connect to different wires
.in(values[i]),
.clk
);
end
endgenerate
尝试使用0初始化clk变量。
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