[英]Compiler bug, or misunderstanding of SystemVerilog? Undeclared port type works in simulation
I have a module with a number of input logic
and output logic
ports, and one port that should be input foo::bar
, where foo is a package, and bar is an enum. 我有一个带有许多
input logic
和output logic
端口的模块,以及一个应该input foo::bar
端口,其中foo是一个包,bar是一个枚举。 But, I left off the input
, so it's just plain foo::bar
. 但是,我没有
input
,所以它只是简单的foo::bar
。 And yet, it still works in simulation (tests pass, and you can see on waveforms that the value is being transmitted correctly). 然而,它仍然可用于模拟(测试通过,您可以在波形上看到值正在正确传输)。
From the LRM , we have: 从LRM ,我们有:
inout_declaration ::=
inout port_type list_of_port_identifiers
input_declaration ::=
input port_type list_of_port_identifiers
| input data_type list_of_variable_identifiers
output_declaration ::=
output port_type list_of_port_identifiers
| output data_type list_of_variable_port_identifiers
interface_port_declaration ::=
interface_identifier list_of_interface_identifiers
| interface_identifier . modport_identifier list_of_interface_identifiers
ref_declaration ::=
ref data_type list_of_port_identifiers
port_type ::=
[ net_type_or_trireg ] [ signing ] { packed_dimension }
It's clearly not inout_dec, input_dec, output_dec, or ref_dec. 它显然不是inout_dec,input_dec,output_dec或ref_dec。 Looking deeper at the LRM,
net_type_or_trireg
is supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wire | wand | wor
深入研究LRM,
net_type_or_trireg
是supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wire | wand | wor
supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wire | wand | wor
supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wire | wand | wor
or tri
, and it's not those. supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wire | wand | wor
或tri
,这不是那些。
Could it be an interface_port_dec? 它可以是interface_port_dec吗? Well,
interface_identifier ::= identifier
and enum_identifier ::= identifier
. 好吧,
interface_identifier ::= identifier
和enum_identifier ::= identifier
。 But, sure := isn't symmetric and transitive, so it's not true that interface_identifier := enum_identifier
. 但是,确定:=不是对称和传递的,所以
interface_identifier := enum_identifier
不是这样。
What am I missing here? 我在这里错过了什么?
It is begin defined as an inout
. 它开始定义为
inout
。
See IEEE Std 1800-2012 § 23.2.2.3 Rules for determining port kind, data type, and direction 请参阅IEEE Std1800-2012§23.2.2.3确定端口类型,数据类型和方向的规则
For the first port in the port list:
对于端口列表中的第一个端口:
— If the direction, port kind, and data type are all omitted, then the port shall be assumed to be a member of a non-ANSI style list_of_ports, and port direction and type declarations shall be declared after the port list.- 如果省略了方向,端口类型和数据类型,则应假定端口是非ANSI样式list_of_ports的成员,并且应在端口列表之后声明端口方向和类型声明。
Otherwise:除此以外:
— If the direction is omitted, it shall default to inout.- 如果省略方向,则默认为inout。
— If the port kind is omitted, it shall be determined as specified below.- 如果省略端口类型,则应按以下规定确定。
— If the data type is omitted, it shall default to logic except for interconnect ports which have no data type.- 如果省略数据类型,除了没有数据类型的互连端口外,它应默认为逻辑。
In the same section after some some examples,t the LRM states: 在一些例子之后的同一部分中, LRM陈述:
For subsequent ports in the port list:
对于端口列表中的后续端口:
— If the direction, port kind and data type are all omitted, then they shall be inherited from the previous port.- 如果省略了方向,端口类型和数据类型,则它们应从前一个端口继承。 If the previous port was an interconnect port, this port shall also be an interconnect port.
如果以前的端口是互连端口,则此端口也应是互连端口。
Otherwise:除此以外:
— If the direction is omitted, it shall be inherited from the previous port.- 如果省略方向,则应从前一个端口继承。
— If the port kind is omitted, it shall be determined as specified above.- 如果省略端口类型,则应按上述规定确定。
— If the data type is omitted, it shall default to logic except for interconnect ports that have no data type.- 如果省略数据类型,除了没有数据类型的互连端口外,它应默认为逻辑。
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