[英]How does SystemVerilog implement the dynamic features of the language?
I have started to learn SystemVerilog and I am reading about the new types, such as: 我已经开始学习SystemVerilog,并且正在阅读有关新类型的信息,例如:
strings 弦
dynamic/associative arrays 动态/关联数组
queues s列
I am wondering how these can be implemented in hardware due to their dynamic nature; 我想知道由于它们的动态特性,如何在硬件中实现它们? is it that they are only for testing/simulation purposes so they are never actually instantiated in hardware? 是它们仅用于测试/模拟目的,因此实际上从未在硬件中实例化吗?
If so, why would you ever use those types of arrays if you had to change to a normal array to run the design on hardware? 如果是这样,如果必须更改为普通阵列以在硬件上运行设计,为什么还要使用这些类型的阵列?
Verilog and now SystemVerilog contain features that fall into two categories: Synthesizable and Non-Synthesizable . Verilog和现在的SystemVerilog包含分为两类的功能: Synthesizableizable和Non-Synthesizable 。 There is no fixed standard that defines which features belong in each catagory. 没有固定的标准来定义每个类别中的哪些功能。 Ideally if you can simulate a feature, you can find a way to synthesize it. 理想情况下,如果可以模拟功能,则可以找到一种综合功能的方法。
Some features wind up in both categories depending on how it's used. 根据使用方式的不同,某些功能在这两个类别中都可以使用。 For example, a for
loop is synthesizable if you can statically determine (ie at compile time rather than run-time) how many iterations it has. 例如,如果您可以静态确定(例如,在编译时而不是在运行时) for
循环有多少次迭代,那么它是可以合成的。 The same is true for a queue or dynamic array - if you can define a maximum size, they can be implemented in hardware. 队列或动态数组也是如此-如果您可以定义最大大小,则可以在硬件中实现它们。
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