How does SystemVerilog implement the dynamic features of the language?

Question

I have started to learn SystemVerilog and I am reading about the new types, such as:

• strings

• dynamic/associative arrays

• queues

I am wondering how these can be implemented in hardware due to their dynamic nature; is it that they are only for testing/simulation purposes so they are never actually instantiated in hardware?

If so, why would you ever use those types of arrays if you had to change to a normal array to run the design on hardware?

Answer 1

Verilog and now SystemVerilog contain features that fall into two categories: Synthesizable and Non-Synthesizable . There is no fixed standard that defines which features belong in each catagory. Ideally if you can simulate a feature, you can find a way to synthesize it.

Some features wind up in both categories depending on how it's used. For example, a for loop is synthesizable if you can statically determine (ie at compile time rather than run-time) how many iterations it has. The same is true for a queue or dynamic array - if you can define a maximum size, they can be implemented in hardware.