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在连续赋值中使用 Verilog Case 语句

[英]Using Verilog Case Statement With Continuous Assignment

I'm trying to perform continuous translation in Verilog from some greycode values to some binary values.我正在尝试在 Verilog 中执行从一些灰色代码值到一些二进制值的连续转换。 That is, I'm trying to take a greycode value coming in on one bus and continually translate it to a binary value on another bus.也就是说,我试图在一条总线上获取一个灰色代码值,并不断将其转换为另一条总线上的二进制值。 I'm trying to do this in Verilog (cannot use SystemVerilog for other reasons).我正在尝试在 Verilog 中执行此操作(由于其他原因无法使用 SystemVerilog)。

I wanted to do something like this:我想做这样的事情:

wire [DATA_SIZE - 1:0] binary_snap;
always @(greycode_snap) begin
case (greycode_snap)
    8'b00000000 : binary_snap = 0;
    8'b00000001 : binary_snap = 1;
    8'b00000011 : binary_snap = 2;
    8'b00000111 : binary_snap = 3;
    8'b00001111 : binary_snap = 4;
    8'b00011111 : binary_snap = 5;
    8'b00111111 : binary_snap = 6;
    8'b01111111 : binary_snap = 7;
    8'b11111111 : binary_snap = 8;
    8'b11111110 : binary_snap = 9;
    8'b11111100 : binary_snap = 10;
    8'b11111000 : binary_snap = 11;
    8'b11110000 : binary_snap = 12;
    8'b11100000 : binary_snap = 13;
    8'b11000000 : binary_snap = 14;
    8'b10000000 : binary_snap = 15;
    default     : binary_snap = 0;
endcase
end

Where greycode_snap is a wire .其中greycode_snapwire

As you may have guessed, this doesn't synthesize and produces the error:您可能已经猜到了,这不会综合并产生错误:

Procedural assignment to a non-register binary_snap is not permitted, left-hand side should be reg/integer/time/genvar

I don't want to change binary_snap to a reg so next I tried this:我不想将binary_snap更改为reg所以接下来我尝试了这个:

wire [DATA_SIZE - 1:0] binary_snap;
assign binary_snap = (greycode_snap == 8'b00000001) ? 1 :
                     (greycode_snap == 8'b00000011) ? 2 :
                     (greycode_snap == 8'b00000111) ? 3 :
                     (greycode_snap == 8'b00001111) ? 4 :
                     (greycode_snap == 8'b00011111) ? 5 :
                     (greycode_snap == 8'b00111111) ? 6 :
                     (greycode_snap == 8'b01111111) ? 7 :
                     (greycode_snap == 8'b11111111) ? 8 :
                     (greycode_snap == 8'b11111110) ? 9 :
                     (greycode_snap == 8'b11111100) ? 10 :
                     (greycode_snap == 8'b11111000) ? 11 :
                     (greycode_snap == 8'b11110000) ? 12 :
                     (greycode_snap == 8'b11100000) ? 13 :
                     (greycode_snap == 8'b11000000) ? 14 :
                     (greycode_snap == 8'b10000000) ? 15 : 0;

Again, greycode_snap is a wire .同样, greycode_snap是一个wire

Which the compiler accepts, but in my (limited) experience I believe this will synthesize into something gross (depending on the synthesis tool used).编译器接受,但根据我的(有限)经验,我相信这会综合成一些粗略的东西(取决于所使用的综合工具)。 So I tried a little optimization:所以我尝试了一些优化:

wire [DATA_SIZE - 1:0] binary_snap;
assign binary_snap = (greycode_snap[0] == 0) ?
                            (greycode_snap[4] == 0) ?
                                (greycode_snap[2] == 0) ?
                                    (greycode_snap[1] == 0) ? 1 : 2
                                : //else
                                    (greycode_snap[3] == 0) ? 3 : 4
                            : // else
                                (greycode_snap[6] == 0) ?
                                    (greycode_snap[5] == 0) ? 5 : 6
                                : // else
                                    (greycode_snap[7] == 0) ? 7 : 8
                        : // else
                            (greycode_snap[4] == 1) ?
                                (greycode_snap[2] == 1) ?
                                    (greycode_snap[1] == 1) ? 9 : 10
                                : //else
                                    (greycode_snap[3] == 1) ? 11 : 12
                            : // else
                                (greycode_snap[6] == 1) ?
                                    (greycode_snap[5] == 1) ? 13 : 14
                                : // else
                                    (greycode_snap[7] == 1) ? 15 : 0;

Again, greycode_snap is a wire .同样, greycode_snap是一个wire

But this code is already extremely convoluted, rigid, and not maintainable.但是这段代码已经非常复杂、死板并且不可维护。

How can I do this in a clean way?我怎样才能以干净的方式做到这一点? It may also be important in the future that this code is expandable.将来,此代码的可扩展性也可能很重要。 If you have any suggestions related to fast greycode counting/translation schemes, those would also be appreciated.如果您对快速灰码计数/翻译方案有任何建议,我们也将不胜感激。

Your code works if you change the declaration of binary_snap from wire to reg .如果您将binary_snap的声明从wire更改为reg您的代码将起作用。 But you can keep it as a wire and use your case statement if you put it into a function.但是您可以将其保留为wire ,如果将其放入函数中,则可以使用case语句。

wire [DATA_SIZE - 1:0] binary_snap;
assign binary_snap = f(greycode);
function [DATA_SIZE - 1:0] f(input [7:0] reg code);
case (code)
    8'b00000000 : f = 0;
    8'b00000001 : f = 1;
    8'b00000011 : f = 2;
    8'b00000111 : f = 3;
    8'b00001111 : f = 4;
    8'b00011111 : f = 5;
    8'b00111111 : f = 6;
    8'b01111111 : f = 7;
    8'b11111111 : f = 8;
    8'b11111110 : f = 9;
    8'b11111100 : f = 10;
    8'b11111000 : f = 11;
    8'b11110000 : f = 12;
    8'b11100000 : f = 13;
    8'b11000000 : f = 14;
    8'b10000000 : f = 15;
    default     : f = 0;
endcase
endfunction

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