Verilog 寄存器不能由原语或连续赋值驱动
[英]Verilog register cannot be driven by primitives or continuous assignment
问题描述
I want to use a module in a test bench like this:
我想在这样的测试台中使用一个模块：
reg [31:0] OutputVal;
reg [15:0] InputVal;
sign theSignExtender(InputVal,OutputVal);
When I compile, I get the error:当我编译时，我收到错误：
error: reg OutputVal;
Any suggestions?有什么建议吗？
1 个解决方案
解决方案1
5 已采纳 2013-11-09 03:21:58
Change:改变：
reg [31:0] OutputVal;
to:到：
wire [31:0] OutputVal;
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