Verilog错误：连续分配左侧的寄存器非法

Question

I'm a verilog noob and I have to do this ALU for a processor but I get this error for this line:

assign SP_out = SP;

"Register is illegal in left-hand side of continuous assignment"

I'm using modelsim.

module ALU(opcode,ra,rb,ra_out,cin,co,res,rst,clk,pc,npc,CCRin,CCRo,SP,SP_out);
  output [1:0] res; // result 
  input wire [7:0]pc;
  output reg [7:0] npc;
  input rst,clk;
  input wire cin;
  input wire [3:0] opcode;
  input wire[1:0] ra;
  input wire[1:0] rb;
  output reg[1:0] ra_out;
  input wire[7:0] SP; // testbench haygebli SP el mafroud yeb2a = 255
  output reg[7:0] SP_out;

  reg[255:0] dmem;

  input wire [3:0] CCRin;
  output reg [3:0] CCRo;
  output co;

  wire [2:0] result; //total result

  assign SP_out = SP;

  assign result = alu_out(ra,rb,cin); 
  assign res = result[1:0];
  assign co = result[2];



  function [2:0] alu_out;
   input [1:0] ra,rb;
   input cin;

  case (opcode)
    0: ;
    4: assign alu_out = ra + rb;
    5: assign alu_out = ra - rb;
    6: assign alu_out = ~(ra & rb);
    7: assign alu_out = {ra[1:0],cin};
    8: assign alu_out = {ra[0],cin,ra[1]};
    10: if (ra == 1)
          begin
         dmem[SP_out] = rb;
         SP_out = SP_out-1;
       end
     else
       begin
       SP_out = SP_out +1;
       rb = dmem[SP_out];
     end
    13: assign ra_out = rb;
    default: begin
    alu_out = 8'bxxxxxxxx; 
    npc = pc+1;


end
endcase 
endfunction
  always@( res)
   begin 
  if (res == 0)
     CCRo[0] = 1;
  else if ( res < 0)
   CCRo[1] = 1;
  else if (co == 1)
    CCRo[2] = 1;
  else if ( res < 0 & res > result)
    CCRo[3] = 1;
  else
    CCRo = CCRin;
end
endmodule

Answer 1

assign statements are only legal on wire types, not reg types.

If you have a reg , then you want to assign it from a block:

always @* begin
   SP_out = SP;
end

Alternatively, remove the reg declaration from SP_out to treat it as a wire, then your assign statement will work.

Both options will behave in the exact same way.