Verilog HDL错误：左侧分配非法

Question

I am learning CPU Design and basic Verilog HDL. I have a processor running in tkgate on Fedora 29 and I have designed a hardware RAM disk. I can't test the RAM but have decided to replace it with an HDL RAM disk. Whenever I try to simulate the circuit, I get the error:
RAM_HDL, line 17: Illegal use of 'w7' in left-hand-side assignment.
Here is my code for the RAM:

module RAM_HDL(RAM, Data_In, Data_Out, Address, RW);  
    reg [15:0] RAM [127:0];  
    wire [15:0] Data_In;  
    wire [15:0] Data_Out;  
    wire [7:0] Address;  
    wire RW;  

    initial  
        $readmemb("RAM_DATA.BIN", RAM);  

    always @(*)  
        begin  
            if (RW)  
                RAM[Address] <= Data_In;  
            Data_Out <= Address;  
        end  

   endmodule  

The error is on line 17:

Data_Out <= Address;  

Answer 1

I believe one of your problems is trying to assign to a wire type in an always block. Try changing the declaration of Data_Out to reg instead of wire. The 2 following examples compiled for me:

module RAM_HDL(Data_In, Data_Out, Address, RW);  
reg [15:0] RAM [127:0];  
input wire [15:0] Data_In;  
output reg [15:0] Data_Out;  
input wire [7:0] Address;  
input wire RW;  

initial  
    $readmemb("RAM_DATA.BIN", RAM);  

always @(*)  
    begin  
        if (RW)  
            RAM[Address] <= Data_In;  
        Data_Out <= Address;  
    end  

endmodule  

note the changes. input and output are declared on the ports. The ram array is not one of the ports and the data_out is a reg.

another option would be to move the assignment of data out outside the always block and keep it as a wire:

module RAM_HDL(Data_In, Data_Out, Address, RW);  
reg [15:0] RAM [127:0];  
input wire [15:0] Data_In;  
output wire [15:0] Data_Out;  
input wire [7:0] Address;  
input wire RW;  

initial  
    $readmemb("RAM_DATA.BIN", RAM);  

always @(*)  
    begin  
        if (RW)  
            RAM[Address] <= Data_In;    
    end  
assign Data_Out = Address;

endmodule  

the changes are mostly the same. the input output declarations and the ram array is removed from the port list. Data_Out however is now assigned outside the always block so it can stay a wire.

Answer 2

The following code compiles at least:

module RAM_HDL(Data_In, Data_Out, Address, RW);

reg [15:0] RAM [127:0];    
input [15:0] Data_In;  
output [15:0] Data_Out;  
input [7:0] Address;  
input RW;  

initial  
  $readmemb("RAM_DATA.BIN", RAM);  

always @(*)  
  begin  
    if (RW)  
      RAM[Address] <= Data_In;  
  end  
assign Data_Out = RAM[Address];  

endmodule