[英]Illegal left hand side of blocking assignment
I am new to verilog. 我是Verilog的新手。 I am writing the code for a 10x16 Round-Shift register.
我正在为10x16舍入移位寄存器编写代码。 Can you help me with the error and also if any optimizations can be done?
您可以协助我解决错误,以及是否可以进行任何优化吗?
module shift_reg_v(
output [15:0] word_out
);
integer i;
integer j;
reg [159:0] coeff;
reg [15:0] word;
initial
begin
for (i=0;i<160;i=i+1)
begin
coeff[i] = 0;
end
for (i=0;i<16;i=i+1)
begin
word[i] = 0;
end
end
always
begin
for (j=0;j < 10;j = j+1)
begin
for (i=0;i < 16;i = i+1)
begin
if (j==0)
begin
word[i] = coeff[(16*(j+1))+i];
end
else
begin
coeff[(16*j)+i] = coeff[(16*(j+1))+i];
end
end
end
coeff[159:144] = word[15:0];
word_out[15:0] = word[15:0];
end
endmodule
The program is showing 2 errors at the output line: word_out[15:0] = word[15:0];
程序在输出行显示2个错误:
word_out[15:0] = word[15:0];
Referring to error: 指错误:
Error -[IBLHS-NONREG] Illegal behavioral left hand side a.sv, 42
错误 -[IBLHS-NONREG]非法行为左侧a.sv,42
Non reg type is not valid on the left hand side of this assignment非注册类型在此分配的左侧无效
The offending expression is : word_out[15:0]令人讨厌的表达式是:word_out [15:0]
Source info: word_out[15:0] = word[15:0];源信息:word_out [15:0] = word [15:0];
The LHS of any procedural assignment statement must be of reg
type. 任何程序分配声明的LHS必须为
reg
类型。 Procedural assignment statements assign values to reg
, integer
, real
, or time
variables and can not assign values to wire
. 过程分配语句将值分配给
reg
, integer
, real
或time
变量,而不能将值分配给wire
。 Note that reg
can hold or store some value depending on some triggering event, while wire
cannot store any value. 请注意,
reg
可以根据某些触发事件来保存或存储某些值,而wire
无法存储任何值。
Make word_out
as reg
as follows: 使
word_out
作为reg
如下:
module shift_reg_v(
output reg [15:0] word_out
);
Referring to the warning: 参考警告:
Warning -[PALF] Potential always loop found a.sv, 24
警告 -[PALF]电位始终循环发现a.sv,24
This always block has no event control or delay statements , it might cause an infinite loop in simulation.该块始终没有事件控制或延迟语句 ,它可能会导致模拟中的无限循环 。
Moreover, you have not given any sensitivity for always
block execution. 此外,您对于
always
执行块还没有任何敏感性。 This might result in infinite loop. 这可能会导致无限循环。 There is no triggering control for
always
block. 没有
always
阻止的触发控制 。 Henceforth the block shall execute infinitely. 此后,该块将无限执行。
Use always @(*)
(or always_comb
in SystemVerilog) for automatic sensitivity list in combinational logic. 将
always_comb
always @(*)
(或SystemVerilog中的always_comb
)用于组合逻辑中的自动灵敏度列表 。
As a side note , you might have a clk
, as clocking input to the module and make the always
block work on the edge of clock . 附带说明一下,作为模块的时钟输入 ,您可能会感到有点
clk
,并使always
模块在时钟的边缘工作。 This will help in modelling sequential logic. 这将有助于对顺序逻辑进行建模。 (Note the usage of nonblocking assignments
<=
in case of sequential logic). (注意,在顺序逻辑的情况下,非阻塞分配的使用
<=
)。
Refer this PDF for difference between reg and nets.Also, this always block might be useful. 请参阅此PDF以了解reg和nets之间的区别。此外, 始终阻止可能有用。
Also, you need to correct following code :- 另外,您需要更正以下代码:-
coeff[i] = 0;
It is a bit assignment and should clearly specify that as coding practice. 这是位分配,应明确指定为编码实践。
coeff[i] = 'h0;
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