Verilog错误：分配左侧的对象必须具有可变数据类型

Question

I'm trying to write a top-level module in Verilog that will open a water valve whenever a sensor reads values below a certain number.

Here is my code:

module ProjectDSD(alteraClock, sensorInput, openValve);

input sensorInput, alteraClock;
output openValve;

always @(sensorInput)
begin

if(sensorInput < 100)       //sensor value to irrigate at
begin

openValve <= 1;  //here

end

else
begin

openValve <= 0;  //here

end
end    
endmodule

Im getting an error saying:

Object "openValve" on left-hand side of assignment must have a variable data type

What am I missing? Also, which pins can I use on an Altera DE2-155 board to output a digital signal of only 1's and 0's for the the valve to open/close?

Answer 1

s/output openValve/output reg openValve/

Outputs default to wire ; you need a reg . See also this question.

Answer 2

openValve is currently inferred as a wire . Add reg openValve; below output openValve; and your code will work.

---

Suggestions: It looks like you are following the IEEE1364-1995 non-ANSI coding style. Will still legal, you might want to change to the ANSI coding style, supported in IEEE1364-2001 and above.

Non-ANSI:

module ProjectDSD(alteraClock, sensorInput, openValve);

input sensorInput, alteraClock;
output openValve;
reg openValve;

ANSI:

module ProjectDSD(
  input alteraClock, sensorInput,
  output reg openValve);

For combinational blocks, it is recommended to use always @* (or the synonymous always @(*) ) instead of always @(sensorInput) . @* is an auto sensitivity list also added in IEEE1364-2001

Answer 3

Try output reg openValve; .

For the second half of your question (which should really be a separate question) import this QSF file into your project. Any of the GPIO can be configured as outputs, and are accessible by the 40-pin header on the side.