[英]Error (10219): Verilog HDL Continuous Assignment error at Mux.v(19): object “muxout” on left-hand side of assignment must have a net type
I want to make Frequency Divider with Counter and MUX. 我想用计数器和MUX制作分频器。
I make 3 module for project 我为项目制作3个模块
// 4-bit Counter // 4位计数器
module Counter (input clk, input reset, output reg[3:0] out);
always@(posedge clk or posedge reset)
begin
if(reset)
out = 4'b0000;
else
begin
if(clk)
if(out < 4'b1111)
out = out + 4'b0001;
else
out = 4'b0000;
end
end
endmodule
//module 4by1 Mux //模块4by1 Mux
module Mux (input [3:0] muxin , input [1:0] sel, output reg muxout);
function _4by1mux;
input [3:0] muxin;
input [1:0] sel;
case (sel)
2'b00 : _4by1mux = muxin[0];
2'b01 : _4by1mux = muxin[1];
2'b10 : _4by1mux = muxin[2];
2'b11 : _4by1mux = muxin[3];
endcase
endfunction
assign muxout = _4by1mux(muxin, sel);
endmodule
//module freqDivider //模块freqDivider
module freqDivider(input clk, input reset, input [1:0] sel, output reg muxout);
wire [3:0]counterbus;
Counter ct1 (clk, reset, counterbus);
Mux mux1 (counterbus, sel, muxout);
endmodule
module freqDivider is top, and I call module Counter and Mux 模块freqDivider位于顶部,我调用模块Counter和Mux
but module Mux has problem with 但是模块Mux有问题
Error (10219): Verilog HDL Continuous Assignment error at Mux.v(19):
object "muxout" on left-hand side of assignment must have a net type
this error 这个错误
ps. ps。 input sel will be changed by time
输入sel将随时间改变
The error is a result of the muxout
output having type reg
instead of type wire
. 该错误是由于
muxout
输出具有reg
类型而不是类型wire
。 In verilog, lines can have two overarching types, either nets (like wire
type) or variables (like reg
types). 在verilog中,线可以具有两种总体类型,即网络(如
wire
类型)或变量(如reg
类型)。 To assign values/logic to net types, you need to use assign
statements and not always
blocks. 要将值/逻辑分配给网络类型,您需要使用
assign
语句,而不always
块。 To assign values/logic to variable types, you can only use always
blocks and not assign
statements. 要将值/逻辑分配给变量类型,只能使用
always
块,不能assign
语句。 So, you can either make your assign
in the Mux
module an always
block or, for an easier solution, don't make the muxout
output a reg
, just leave out the reg
keyword and it will be a wire
. 因此,您可以在
Mux
模块中将您的assign
always
阻塞,或者,为了更简单的解决方案,不要将muxout
输出设置为reg
,而只需忽略reg
关键字,它将成为wire
。
Error is that you have declared mux_out
as reg type, instead of wire type. 错误是您已将
mux_out
声明为reg类型,而不是wire类型。 Default type of any port is wire. 任何端口的默认类型是wire。 You are doing continuous assignment on that net through
assign
keyword. 您正在通过
assign
关键字对该网络进行连续分配。 And on reg
type nets, assignment can only be done inside procedural block (initial, always). 在
reg
类型的网络上,赋值只能在程序块内部进行(初始的,始终是)。
Change to mux_out
from output reg
to output
only. 从
output reg
更改为mux_out
,仅output
。
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