[英]I am getting error when check my systemverilog code in quartus II
I have this simple code checked with Quartus II.我用 Quartus II 检查了这个简单的代码。 First, It gives me error 5000 iterations for loop limit then I try to change verilog constant loop limit variable in settings and now it is giving me this error
首先,它给了我循环限制的错误 5000 次迭代然后我尝试在设置中更改 verilog 常量循环限制变量,现在它给了我这个错误
Error (293007): Current module quartus_map ended unexpectedly.错误 (293007):当前模块 quartus_map 意外结束。 Verify that you have sufficient memory available to compile your design.
验证您是否有足够的 memory 可用于编译您的设计。 You can view disk space and physical RAM requirements on the System and Software Requirements page of the Intel FPGA website ( http://dl.altera.com/requirements/ ).
您可以在英特尔 FPGA 网站 ( http://dl.altera.com/requirements/ ) 的系统和软件要求页面上查看磁盘空间和物理 RAM 要求。
Is this something related to tool limitation or am I doing something wrong with my code?这与工具限制有关还是我的代码有问题?
Here is my code:这是我的代码:
module Branch_status_table #(parameter BST_length = 16383) //16383
(
output reg [2:1] status,
output reg [32:1] PC_predict_o,
input wire [2:1] status_update,
input wire [32:1] PC_in, PC_update,
input wire [32:1] PC_predict_update,
input wire clk,en_1,RST
);
wire [14:1] PC_index, PC_index_update;
//Internal memory
reg [2:1] status_bits [BST_length:0];
reg [32:1] PC_predict [BST_length:0];
reg [16:1] PC [BST_length:0];
//Combinational
assign PC_index = PC_in [16:3];
assign PC_index_update = PC_update [16:3];
//
initial begin
for ( int i=0; i <= BST_length; i=i+1) begin
status_bits[i] <= 0;
PC_predict[i] <= 0;
PC[i]<=0;
end
end
//Prediction
always_ff @(posedge clk) begin
if ( (PC[PC_index]==PC_in[32:17]) && (status_bits[PC_index]!=0) ) begin
status <= status_bits [PC_index];
PC_predict_o <= PC_predict [PC_index];
end
else begin
status <= 0;
PC_predict_o <= 0;
end
end
//Update
always_ff @(posedge clk) begin
if (en_1==1) begin
status_bits[PC_index_update] <= status_update;
PC [PC_index_update] <= PC_update[32:17] ;
PC_predict[PC_index_update] <= PC_predict_update;
end
else begin
status_bits[PC_index_update] <= status_bits[PC_index_update] ;
PC [PC_index_update] <= PC [PC_index_update] ;
PC_predict[PC_index_update] <= PC_predict[PC_index_update] ;
end
end
endmodule
There is at one least coding issue here and maybe a resource utilization issue.这里至少有一个编码问题,可能还有资源利用问题。
The coding issue:编码问题:
Your code is inferring block ram, and trying to initialize/reset it.您的代码正在推断块 ram,并尝试初始化/重置它。
In general you can't reset block rams using a single initial block.通常,您不能使用单个初始块来重置块 ram。
That style of initialization can be done in a testbench, not in RTL.这种初始化风格可以在测试台中完成,而不是在 RTL 中。
Synthesis tools have physical limits.合成工具有物理限制。
To reset/initialize a block ram you must write 0 to each address.要重置/初始化块 RAM,您必须将 0 写入每个地址。 You must use the same type of synchronous process (always @(posedge clk)) because the memory is a synchronous device.
由于 memory 是同步设备,因此您必须使用相同类型的同步进程(始终为 @(posedge clk))。 Put a mux in front of the write port and use a state machine a start up to write 0's to every address, then when the state machine finishes that move to a operational state where the BRAM behaves like you normally want it to.
在写入端口前面放置一个多路复用器,并使用 state 机器启动以将 0 写入每个地址,然后当 state 机器完成时,移动到可操作的 Z9ED39E2EA931586B6A985A6942EF57
This page discusses the issue.本页讨论了这个问题。
https://www.edaboard.com/threads/how-to-clear-reset-my-bram-in-vhdl-xilinx.247572/ https://www.edaboard.com/threads/how-to-clear-reset-my-bram-in-vhdl-xilinx.247572/
This is a Xilinx related answer;这是 Xilinx 相关的答案; other vendors work the same way.
其他供应商的工作方式相同。
Summarizing the coding issue: You probably don't need to initialize and you can't do it this way:总结编码问题:您可能不需要初始化,也不能这样做:
initial begin
for ( int i=0; i <= BST_length; i=i+1) begin
status_bits[i] <= 0;
PC_predict[i] <= 0;
PC[i]<=0;
end
end
Potential Utilization Issue:潜在利用问题:
FPGAs' have finite resources. FPGA 的资源是有限的。
The tool may be trying to indicate the code infers more block ram than the part has.该工具可能试图指示代码推断出的块 RAM 比零件具有的更多。 To verify this premise, change parameter BST_length from 16K to something small like 8 and see if the utilization issue ("insufficient memory) goes away. If it goes away then you need to re-design with less memory.
为了验证这个前提,将参数 BST_length 从 16K 更改为像 8 这样的小值,看看利用率问题(“内存不足)是否消失。如果它消失了,那么你需要用更少的 memory 重新设计。
You could also analyze this by hand by understanding how much BRAM the part has and how much you are attempting to infer.您还可以通过了解零件有多少 BRAM 以及您试图推断多少来手动分析这一点。 Don't infer more than the part has.
不要推断出超出部分的内容。
I think the tool is confused because of two issues related to the same inference of BRAM.我认为该工具由于与 BRAM 的相同推断相关的两个问题而感到困惑。 When you change your code a little the tool switches trying to tell you about the other issue.
当您稍微更改代码时,工具会切换以尝试告诉您其他问题。
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