在Verilog生成语句中增加多个Genvars

Question

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in a single generate loop. I'm trying the following:

genvar i,j;
//Level 1
generate
  j=0;
  for (i=0;i<128;i=i+1)
  begin: level1Comp
    assign ci1[i] = minw(tc[j],tc[j+1]);
    j = j+2;
  end
endgenerate

And getting the following error:

Error-[SE] Syntax error
  Following verilog source has syntax error :
  "encoder.v", 322: token is '='
    j=0;

Anyone know how to increment multiple genvars in the same generate statement? Or at least get equivalent functionality?

Answer 1

Anyone know how to increment multiple genvars in the same generate statement?

This is not allowed because a generate for loop creates an implicit localparam statement for the loop variable and elaborates the items in the loop based only on that localparam. This means any items inside the loop must be valid outside the loop if the genvar was declared as a localparam.

genvar i,j;
//Level 1
generate
  j=0;
  for (i=0;i<128;i=i+1)
  begin: level1Comp
    assign ci1[i] = minw(tc[j],tc[j+1]);
    j = j+2;
  end
endgenerate

becomes

//Done for each value of i
genvar j;
localparam integer i = i_for_each_iteration;

j=0; //Not valid outside a procedural context so modelsim complains
assign ci1[i] = minw(tc[j],tc[j+1]);
j = j+2; //Also not valid outside a procedural context

In this case you could create a 'constant' value dependent on the genvar using an explicit parameter inside the loop.

genvar i;
//Level 1
generate
  for (i=0;i<128;i=i+1)
  begin: level1Comp
    localparam integer j = i*2;
    assign ci1[i] = minw(tc[j],tc[j+1]);
  end
endgenerate

Answer 2

Assuming that ci1 has half the depth of tc and you want, say ci1[0] = min(tc[0], tc[1]) , ci[1] = min(tc[2], tc[3]) etc, the following should work:

module st_genvar();

  int ci1 [0:127];
  int tc [0:255];

  function int minw(int i1, int i2);
      if(i1 < i2 )
        minw = i1;
      else
        minw = i2;
  endfunction

  genvar i;
  //Level 1
  generate
      for (i=0;i<128;i=i+1)
        begin: level1Comp
            assign ci1[i] = minw(tc[i*2],tc[i*2+1]);
        end
  endgenerate

endmodule