compare multiple values with a variable in SystemVerilog

Question

I have logic to compare a variable with multiple values. For example:

logic [3:0] a;
always_comb begin
    flag = (a == 'd13) || (a == 'd2) || (a=='d1); //can this be simplified?
end

Is there a easy way to write this statement?

Answer 1

This is more concise using the inside operator:

always_comb begin
    flag = (a inside {1, 2, 13});
end

This is more scalable as well, allowing you to easily add or remove values from the set.

The syntax also supports ranges of values:

    flag = (a inside {[1:2], 13});

Refer to IEEE Std 1800-2017, section 11.4.13 Set membership operator.

Since the values in the set are all constants, it should be synthesizable (but YMMV).