如何在凿子中对寄存器的向量进行参数化

Question

I need an example on how to paramtrize Vector of registers in terms of bit-width and initial values which are not '0' and are different for each register.

My use-case is a generic filter coefficients bank with some unique reset values to each, and off course an option to override values. I thought of something like the below code (not really sure how to write the iteration, so this is kind of pseudo):

class Coeffbank(bitWidth : UInt ,ncoeff : UInt, rstVal : Vec(SInt)) extends Module {
    // how do iterate through the reset vector ?? //
    val coeffs   = Vec.fill(ncoeff) {Reg(init = SInt(rstVal(i),width = bitwidth))
}

Also, when new'ing the above (instantiating this module how do I pass the list of reset value in the argument list?

Hoping to get some help on how to write it properly.

Answer 1

The explanation should probably be a bit more thorough, but basically you need to create a Reg of Vec . Something like should do it:

val coeffs = RegInit(rstVal)

In this case, since you already have the Vec of reset values, you can just pass it to the Reg constructor.

I'm assuming that the size of rstVal is equal to ncoeff , otherwise you'll need to reduce the size of rstVal with something like rstVal.take(ncoeff) . Also note that I'm using RegInit which is the preferred way to create a register with a reset value.

Answer 2

Let's start with the easy case. This would be much easier if instead of a Vec of SInt s your rstVa l array was instead a scala collection ( Seq , Array , ...) of regular SInt. When possible it is best to save generation of actual hardware until you directly need them. If rstVal contains Int's. Your code would become

 val newRstVals = VecInit(Seq.tabulate(ncoeff) { index => rstVals(index).S(bitWidth.W) })
 val reg = RegInit(newRstVals)

If you really need to pass in a Vec then the right approach is to create a separate type instance and use the two argument call to RegInit

val vecType = Vec(ncoeff, SInt(bitWidth.W))
val newRstVals1 = VecInit(Seq.tabulate(ncoeff) { index => newRstVals(index) })
val reg = RegInit(vecType, newRstVals1)

There might be problems if the bitWidth you pass in is not big enough to contain the constants you have passed in. You probably should have some checks for that.