在 vhdl 中创建 1 位 ALU

Question

The following problem is a homework.

I need to create an 1-bit slice ALU that can do the following between two 1 bit inputs: and, or, addition using full adder, subtraction by using addition and inverting the inputs, xor. I need a 4 to 1 multiplexer to choose between the those functions of the alu.

This picture summarizes what I need to create

I am asked to do this with with hierarchical design(structural). So, I need to create components. This is the part one of the whole project. In the second part I need to use this 1 bit ALU to create a 16 bit ALU. But my question for now is focused on the first part.

I have created an and gate, or gate, ADD for full adder, two not gates to invert inputs and mux 4 to 1.

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Entity or & and 

ENTITY orGate IS
    PORT( a, b: in std_logic;
        s: out std_logic);
END orGate;

ARCHITECTURE structure OF orGate IS
BEGIN
    s <= a OR b;
END structure;

ENTITY andGate IS
    PORT( a, b: in std_logic;
        s: out std_logic);
END andGate;

ARCHITECTURE structure OF andGate IS
BEGIN
    s <= a AND b;
END structure;

--Entity add 

ENTITY ADD IS
PORT(   cin, a, b : in std_logic;
        s, cout     : out std_logic)
END ADD;

ARCHITECTURE structure OF ADD IS
BEGIN
    s <= (a AND (NOT b) AND (NOT cin)) OR ((NOT a) AND b AND (NOT 
cin)) OR ((NOT a) AND (NOT b) AND cin) OR (a AND b AND cin);
    cout <=( a AND b) OR (cin AND a) OR (cin AND b);
END ADD

-- Inverter, Sub, nor

ENTITY notB IS
    PORT( b: in std_logic;
        s: out std_logic);
END notB;

ARCHITECTURE structure OF notB IS
BEGIN
    s <= NOT b;
END structure;

ENTITY notA IS
    PORT( a: in std_logic;
        s: out std_logic);
END notA;

ARCHITECTURE structure OF notA IS
BEGIN
    s <= NOT a;
END structure;

ENTITY xorGate IS
    PORT( a, b: in std_logic;
        s: out std_logic);
END xorGate;

ARCHITECTURE structure OF xorGate IS
BEGIN
    s <= a XOR b;
END structure;

-- MUX 4 TO 1

ENTITY mux4 IS
PORT(
    andGate      : in  std_logic_vector(2 downto 0);
    orGate      : in  std_logic_vector(2 downto 0);
    sum      : in  std_logic_vector(2 downto 0);
    xorGate      : in  std_logic_vector(2 downto 0);
    operation     : in  std_logic_vector(1 downto 0);
    rslt       : out std_logic_vector(2 downto 0));
END mux4;

ARCHITECTURE rtl OF mux4 IS
BEGIN
WITH operation SELECT
        rslt <= andGate WHEN "00",
        orGate WHEN "01",
        sum WHEN "10",
        xorGate WHEN OTHERS;
end rtl;

So my question is: How can I use components and then put all these together to create a functioning 1 bit alu? Also, I am not sure about A inverter and B inverter because in the picture there are 2 mux of 2 to 1.

Answer 1

Use the structure COMPONENT to add the entities you just described between the ARCHITECTURE and BEGIN keywords of your final entity.

Once you've done that, you will have to bind the components between them using signals. You have as much signals as wires in your provided graph.

Here an example : https://www.doulos.com/knowhow/vhdl_designers_guide/components_and_port_maps/