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如何在一个FPGA上实现多个独立的器件?

[英]How to implement several independent devices on one FPGA?

I need implement 2 or more independent device on FPGA (Altera Cyclone III).我需要在 FPGA (Altera Cyclone III) 上实现 2 个或更多独立设备。 For example: two counters by one and by two.例如:两个计数器一一二。 How I do this make?我怎么做这个? And how to use this devices parallel?以及如何并行使用此设备? Thanks everybody!谢谢大家!

Everything happens in parallel on an FPGA.一切都在 FPGA 上并行发生。 Heres an example solution in verilog这是 verilog 中的示例解决方案

Counter Module计数器模块

module counter #(
    parameter pCntNum =1
    ) (
    input iClk,
    input iRst,

    output reg [7:0] oCnt
);
always @ (posedge iClk)
    if (iRst) begin
        oCnt <=0;
    end else begin
        oCnt <= oCnt +pCntNum;
    end    
endmodule

Top module顶部模块

module top (
    input iClk,
    input iRst,

    output [7:0] oCntBy1,
    output [7:0] oCntBy2
);

    //Instantiate count by 1 module
    counter #(
        .pCntNum(1)
    )counter_by_1_inst(
        .iClk(iClk),
        .iRst(iRst),
        .oCnt(oCntBy1)
    );

    //Instantiate count by 2 module
    counter #(
        .pCntNum(2)
    )counter_by_2_inst(
        .iClk(iClk),
        .iRst(iRst),
        .oCnt(oCntBy2)
    );
endmodule

There are many many ways to do this, however I gave a solution which I think best exemplifies what you are asking.有很多方法可以做到这一点,但是我给出了一个解决方案,我认为它最能说明您的要求。

EDIT: I just saw the tag for VHDL and not Verilog.编辑:我刚刚看到了 VHDL 而不是 Verilog 的标签。 The same approach and mechanisms apply to a VHDL solution,however Quartus accepts both Verilog and VHDL source files (You can even have a code base with both).相同的方法和机制适用于 VHDL 解决方案,但 Quartus 接受 Verilog 和 VHDL 源文件(您甚至可以拥有包含两者的代码库)。 With a simple VHDL tutorial you will be able to create a solution equivalent to the Verilog one I wrote if need be.如果需要,通过一个简单的 VHDL 教程,您将能够创建一个与我编写的 Verilog 等效的解决方案。

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