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我如何将信号输出生成为慢时钟域的倍数？

[英]How could I generate signal output as a slow clock domain that is a multiple of a fast clock domain?

原文 2019-08-22 21:30:52 5 1 vhdl/ clock/ digital

I have an FPGA which I have 40-60 MHz clock domain I am working with.我有一个 FPGA，我正在使用它的 40-60 MHz 时钟域。 My output will be a slow multiple of that clock domain.我的输出将是该时钟域的慢倍数。

So if I have 40 MHz oscillator, the output interface would be 5 MHz.所以如果我有 40 MHz 的振荡器，输出接口将为 5 MHz。

I was planning on using a clock divide by 2 and sending the signal to the input, but I don't like this design because I read about how I would need to send the signals through a clock buffer which I may not have enough resources and others have stated it could create hold violations.我计划使用时钟除以 2 并将信号发送到输入，但我不喜欢这种设计，因为我阅读了有关如何通过时钟缓冲区发送信号的信息，而我可能没有足够的资源和其他人则表示这可能会造成违规。 ( https://www.thecodingforums.com/threads/pulse-stretching.377607/ ) ( https://www.thecodingforums.com/threads/pulse-stretching.377607/ )

My second idea is to use a counter that counts the amount of time required to hold the Q output of a DFF and apply back pressure to source logic.我的第二个想法是使用一个计数器来计算保持 DFF 的 Q 输出并将背压施加到源逻辑所需的时间量。

I currently do not have code.我目前没有代码。 I am still thinking of it conceptually.我还在概念上考虑它。

The initial plan was use several clock divide by 2 block in series to get the output desired.最初的计划是使用多个时钟除以 2 块串联以获得所需的输出。

For signals that seem like a 5 MHz clock domain but were generated with a 40 MHz clocked system, what is the terminology for this type of clock domain crossing?对于看起来像 5 MHz 时钟域但由 40 MHz 时钟系统生成的信号，这种类型的时钟域交叉的术语是什么？

Are there any other options?还有其他选择吗？

Thank You谢谢你

1 个解决方案

这是一个同步 CDC，计数器方法属于一类基于 FSM 的时钟分频器。

当我将数据从慢速时钟域传输到快速时钟域时，拉伸后的数据不是处理的问题吗？ - When I cross data from a slow clock to a fast clock domain, wouldn't the stretched data be an issue for processing?

如何将时钟驱动到单个时钟域？ - How to drive a clock to a single clock domain?

不同的时钟域 VHDL - Different Clock Domain VHDL

VHDL：基于非常快的时钟创建非常慢的时钟脉冲 - VHDL: creating a very slow clock pulse based on a very fast clock

在VHDL中将输出信号延迟3个时钟周期 - Delay output signal for 3 clock cycles in VHDL

如何生成具有这些规范的 I²C 时钟？ - How do I generate an I²C clock with these specs?

如何在VHDL中将信号延迟几个时钟周期 - how to delay a signal for several clock cycles in vhdl

在VHDL中，如果信号不是时钟，我可以使用signal'event吗？ - In VHDL, Can I use signal'event if signal is not a clock?

如何为不同寄存器总线宽度选择时钟跨域的触发器数量？ - How to select the number of flop for clock cross domain for different register bus width?

模拟是否总是在时钟沿显示信号/输出分配？ - Does simulation always show signal/output assignment on clock edge?

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相关问题 当我将数据从慢速时钟域传输到快速时钟域时，拉伸后的数据不是处理的问题吗？ - When I cross data from a slow clock to a fast clock domain, wouldn't the stretched data be an issue for processing? 如何将时钟驱动到单个时钟域？ - How to drive a clock to a single clock domain? 不同的时钟域 VHDL - Different Clock Domain VHDL VHDL：基于非常快的时钟创建非常慢的时钟脉冲 - VHDL: creating a very slow clock pulse based on a very fast clock 在VHDL中将输出信号延迟3个时钟周期 - Delay output signal for 3 clock cycles in VHDL 如何生成具有这些规范的 I²C 时钟？ - How do I generate an I²C clock with these specs? 如何在VHDL中将信号延迟几个时钟周期 - how to delay a signal for several clock cycles in vhdl 在VHDL中，如果信号不是时钟，我可以使用signal'event吗？ - In VHDL, Can I use signal'event if signal is not a clock? 如何为不同寄存器总线宽度选择时钟跨域的触发器数量？ - How to select the number of flop for clock cross domain for different register bus width? 模拟是否总是在时钟沿显示信号/输出分配？ - Does simulation always show signal/output assignment on clock edge?

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