[英]SystemVerilog Using Array of Interfaces
I'm trying to implement a parametric syntheizable bus multiplexer using interfaces in SystemVerilog.我正在尝试使用 SystemVerilog 中的接口实现参数化可合成总线多路复用器。 Below, I have a reduced implementation of the interface and the mux.
下面,我简化了接口和复用器的实现。 The mux has an array of slave interfaces in its port definition:
多路复用器在其端口定义中有一组从接口:
interface bus_if();
logic req;
logic [31:0] addr;
modport master ( output req, addr );
modport slave ( input req, addr );
endinterface
module mux #(
parameter int N_SLAVES = 4
) (
bus_if.slave master,
bus_if.master slave[N_SLAVES]
);
...
endmodule
In the top level, I try to crate a bus mux like this:在顶层,我尝试创建一个像这样的总线复用器:
module top;
bus_if master(), slave1(), slave2();
mux #(
.N_SLAVES ( 2 )
) bus_mux ( master
.master ( data_if ),
.slave ( '{slave1, slave2 }) <-- Error here in Cadence Xcelium
);
endmodule
This works perfectly fine in ModelSim.这在 ModelSim 中工作得很好。 However, trying this for example in Cadence Xcelium, this fails with
An instance name is not a legal rvalue
.但是,例如在 Cadence Xcelium 中尝试此操作时,会失败
An instance name is not a legal rvalue
。
So the question: Am I just using something Modelsim supports and Xcelium not?所以问题是:我只是使用 Modelsim 支持而 Xcelium 不支持的东西吗? And how to fix this to make it work in both?
以及如何解决这个问题以使其在两者中都能正常工作?
It looks like the standard does not allow use of interfaces in '{...}
patterns.看起来标准不允许在
'{...}
模式中使用接口。 Modelsim is in violation of the standard. Modelsim 违反了标准。
One way of implementing it is to use parameterized interface:实现它的一种方法是使用参数化接口:
interface bus_if#(N_SLAVES=1)();
logic req[N_SLAVES];
logic [31:0] addr[N_SLAVES];
modport master ( output req, addr );
modport slave ( input req, addr );
endinterface
module mux #(
parameter int N_SLAVES = 4
) (
bus_if.slave slave,
bus_if.master master
);
assign master.req[0] = slave.req[1];
// ...
endmodule
module top;
bus_if master();
bus_if #(.N_SLAVES(2)) slave();
mux #(
.N_SLAVES ( 2 )
) bus_mux (
.master ( master ),
.slave ( slave )
);
endmodule
this way it works in cadence and synopsys.这样它就可以在 cadence 和 Synopsys 中工作。 No idea about the modelsim though.
虽然不知道modelsim。
It is simply resolved as below.简单解决如下。
module top;
bus_if master(),
bus_if slave[0:1]();
mux #(
.N_SLAVES ( 2 )
) bus_mux ( master
.master ( data_if ),
.slave ( slave )
)
endmodule
You'd better using modport, not just wire as you do.你最好使用 modport,而不仅仅是像你那样接线。 It might occure synthesis problems.
可能会出现合成问题。
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