SystemVerilog Using Array of Interfaces

Question

I'm trying to implement a parametric syntheizable bus multiplexer using interfaces in SystemVerilog. Below, I have a reduced implementation of the interface and the mux. The mux has an array of slave interfaces in its port definition:

interface bus_if();
  logic req;
  logic [31:0] addr;

  modport master (  output req, addr );
  modport slave ( input  req, addr );
endinterface

module mux #(
  parameter int N_SLAVES = 4
  ) (
    bus_if.slave  master,
    bus_if.master slave[N_SLAVES]
  );
  ...
endmodule

In the top level, I try to crate a bus mux like this:

module top;
  bus_if master(), slave1(), slave2();
  mux #(
    .N_SLAVES ( 2 )
  ) bus_mux ( master
    .master ( data_if ),
    .slave  ( '{slave1, slave2 }) <-- Error here in Cadence Xcelium
  );
endmodule

This works perfectly fine in ModelSim. However, trying this for example in Cadence Xcelium, this fails with An instance name is not a legal rvalue .

So the question: Am I just using something Modelsim supports and Xcelium not? And how to fix this to make it work in both?

Answer 1

It looks like the standard does not allow use of interfaces in '{...} patterns. Modelsim is in violation of the standard.

One way of implementing it is to use parameterized interface:

interface bus_if#(N_SLAVES=1)();
  logic req[N_SLAVES];
  logic [31:0] addr[N_SLAVES];

  modport master (  output req, addr );
  modport slave ( input  req, addr );
endinterface

module mux #(
  parameter int N_SLAVES = 4
  ) (
    bus_if.slave  slave,
    bus_if.master master
  );
  assign master.req[0] = slave.req[1];
//  ...
endmodule

module top;
  bus_if master();
  bus_if #(.N_SLAVES(2)) slave(); 
  mux #(
    .N_SLAVES ( 2 )
  ) bus_mux ( 
    .master ( master ),
    .slave  ( slave ) 
  );
endmodule

this way it works in cadence and synopsys. No idea about the modelsim though.

Answer 2

It is simply resolved as below.

module top; 
  bus_if master(), 
  bus_if slave[0:1](); 
  mux #( 
    .N_SLAVES ( 2 ) 
  ) bus_mux ( master 
      .master ( data_if ), 
      .slave  ( slave   )
  )
endmodule

You'd better using modport, not just wire as you do. It might occure synthesis problems.