SystemVerilog Array of Bits to Int Casting

Question

I have the following SystemVerilog variable:

bit [5:0] my_bits = 6'h3E;            // my_bits == 6'd62

I want to take the bit-wise inverse of it and then get that result into an int variable, treating the underlying bits as unsigned, so first I did this:

bit [5:0] my_bits_inv = ~my_bits;     // my_bits_inv = 6'b00_0001
int       my_int = int'(my_bits_inv); // my_int = 1

That gave me what I wanted. However, if I combine the inversion and casting into a single step, I get -63:

int       my_int2 = int'(~my_bits); // my_int2 = -63 ???

Presumably it is treating my_bits as 32 bits, then taking the inverse of that to give int'(~32'h0000_003E) = int'(32'hFFFF_FFC1) = -63 .

Can someone explain why this happens? Does it have to do with self-determination rules?

Answer 1

Your diagnosis is correct. This is explained in IEEE Std 1800-2017, section 11.6.1 Rules for expression bit lengths . In your case, casting with int' expands my_bits to match the width of int (32) before the bitwise inversion.

Consider also:

$displayb(~my_bits);
$displayb(int'(~my_bits));

Outputs:

000001
11111111111111111111111111000001