VHDL将自定义类型签名的integer转换为std_logic_vector

Question

Hi I have a signal that is used in many places and subject to being altered down the track. So to simplify maintenance I have made a TYPE declaration called T_RowInt.

I have made two signals "typed" and "untyped" which both equate to an integer range -63 to 63 to demonstrate the problem.

Code follows:

type T_RowInt is range -63 to 63;
signal typed : T_RowInt;
signal untyped : integer range -63 to 63;

signal text_col : integer range 0 to 127 := 0;
signal bank : std_logic_vector(2 downto 0) := "111";
signal page : std_logic_vector(3 downto 0) := "0000";

I use the above in the following expressions:

addr_r_dram(19 downto 0)<= bank & page & std_logic_vector(to_unsigned(typed,6)) & std_logic_vector(to_unsigned(text_col, 7));

This fails syntax checking with "to_unsigned can not have such operands in this context" However, this expression:

addr_r_dram(19 downto 0)<= bank & page & std_logic_vector(to_unsigned(untyped,6)) & std_logic_vector(to_unsigned(text_col, 7));

Is ok

Is there a way to force conversion of a custom TYPED signal?

Thanks

Mark

Answer 1

If you use type then you have defined a completely new type as far as VHDL is concerned. However, how about using a subtype , eg

subtype T_RowInt is integer range -63 to 63;

then VHDL will not consider T_RowInt as being a completely different type. Your signal untyped is actually using a subtype, a so-called _anonymous subtype`:

signal untyped : integer range -63 to 63;

Perhaps you can see the similarity between these two lines of code?