如何在Verilog中更改时钟？

Question

module task_A(input [15:0]sw, input clk,output reg [3:0] an= 4'b1111,output reg[7:0] seg);
reg [2:0] num = 3'd0;
wire Z,Z1,Z2;
clk_1_47hz(clk,Z1);
clk_762hz(clk,Z2);
reg count=0;
assign Z= (count<5)?(Z1):(Z2);
always @ (posedge Z)
begin
num <= (sw[15:0]==16'b1111111111111111)?((num==5 | num==0)?(3'd1):(num+1)):(0);
count <=count+1;
case(num)
    3'd0 : begin seg <= 8'b11111111 ; an <= 4'b1111; end
    3'd1 : begin seg <= 8'b10000111 ; an <= 4'b0111; end //t
    3'd2 : begin seg <= 8'b10001000 ; an <= 4'b1011; end //a
    3'd3 : begin seg <= 8'b11001111 ; an <= 4'b1101; end //l
    3'd4 : begin seg <= 8'b11111001 ; an <= 4'b1101; end //l
    3'd5 : begin seg <= 8'b10010001 ; an <= 4'b1110; end //y
    
    endcase
    end
endmodule

I wish to change the clock after the 7 segment display has displayed 'tally' once. So I use count to check. But the clock does not change at all. May I know how to correct it?

Answer 1

count is declared as a 1-bit signal, which is always smaller than 5.

reg count=0;

To accomplish your goal, declare it as a 3-bit signal or more.
And you may also need to set a limit for count , and stop it, if you want to switch to Z2 clock forever after 'tally' is displayed once.