计数器的输出未显示为在 Verilog 模拟中初始化

Question

I'm having some trouble running a simulation to make sure my counter works. The code for my counter is:

module counter(
    input clk, rst,
    output reg [16:0] counterout
    );
always @(posedge(clk), posedge(rst))
begin
     if (rst) counterout <= 0;
     else if (clk) counterout <= counterout + 1;
end
endmodule

and my testbech code:

`timescale 1ns / 1ps
module testbench();

reg clock;
reg rst;
wire [16:0] out;

counter test(
    .clk(clock),
    .rst(rst),
    .counterout(out)
);

integer k = 0;

initial
begin
    rst = 0;
    clock = 0;
    #100 ;
    
    for(k = 0; k < 1000; k = k+1)
    begin
        #5 clock = clock + 1;
    end
    #5 $finish;
end
endmodule

Unfortunately, when I run the simulation, it shows the output as never initialized. Any idea why?

Answer 1

Your counter remains unknown because you did not reset it. The counter needs the rst signal to be 1 to be reset, but your testbench always drives rst as 0. Here is one way to change the testbench to reset the counter.

initial
begin
    rst = 1; // Assert reset
    clock = 0;
    #100 ;
    rst = 0; // Release reset

    for(k = 0; k < 1000; k = k+1)
    begin
        #5 clock = clock + 1;
    end
    #5 $finish;
end