尝试将我的 verilog 代码从 modelsim 传输到 quartus 时出现很多错误

Question

Hi guys I built a simple design in modelsim with a lot of verilog file. I am trying to get a RTL schematic so i want to tranfer my project to quartus. But i got a lot of errors even my code run ok on modelsim.

module OR_64BITS (out, in1, in2);
  input wire [63:0] in1, in2;
  output wire [63:0] out;
  
  genvar i;
    generate
        for (i = 0; i < 64; i = i + 1) begin
      or (out[i], in1[i], in2[i]);
        end
    endgenerate 
endmodule

i got this error Error (10644): Verilog HDL error at basic_components_2.v(9): this block requires a name on this line

for (i = 0; i < 64; i = i + 1) begin

Please help me. Thank you.

Answer 1

I have a verilog standard pdf file with the version: IEEE Std 1364-2001, 28 September 2001.

In it, I can find the standard BNF definition for generate - for block:

generate_loop_statement ::=
  for ( genvar_assignment ; constant_expression ; genvar_assignment )
    begin : generate_block_identifier { generate_item } end

According to it, the : generate_block_identifier part is required.

You can modify your code as @David Shah suggested in comment. Add : a_uniq_block_name to that for(...) line.

EDIT:
I have this verilog-2001 standard doc only. As @Matthew Taylor commented, this requirement has been removed in IEEE Std 1364-2005. Maybe you can find which standard version your quartus comply with in some deep dialogs.