[英]D FlipFlop sequence generator for the sequence 1101011 does not generate results
I have created a module for DFlipFlop in DFF
module and instantiated 4 of them in seqgen
module.我在
DFF
模块中为 DFlipFlop 创建了一个模块,并在seqgen
模块中实例化了其中的 4 个。 I am not able to generate results.我无法生成结果。 Can you please help me where I am going wrong?
你能帮我解决我哪里出错了吗?
module DFF(input d, input rstn, input clk, output reg q);
always @(posedge clk or negedge rstn)
if(!rstn)
q <= 0;
else
q <= d;
endmodule
module seqgen();
wire q1=1'b1,q2=1'b1,q3=1'b1,q4=1'b0;
wire da=1'b1;
reg clk = 1'b0,rstn = 1;
always #10 clk = ~clk;
assign da = ~q1|~q2|~q4;
DFF dffa(da,rstn,clk,q1);
DFF dffb(q1,rstn,clk,q2);
DFF dffc(q2,rstn,clk,q3);
DFF dffd(q3,rstn,clk,q4);
endmodule
There are 2 types of problems.有两种类型的问题。
The outputs of your DFF
modules are being driven from within the DFF
module and from within the seqgen
module due to the continuous wire
assignment.由于连续
wire
分配,您的DFF
模块的输出是从DFF
模块和seqgen
模块内部驱动的。 You should not assign a value to the wire
.您不应该为
wire
分配值。 This causes contention which is one source of the unknown values ( x
) on the outputs.这会导致争用,这是输出上未知值 (
x
) 的来源之一。 In the case of da
, you have 2 continuous assignments, but you should only have 1.在
da
的情况下,您有 2 个连续分配,但您应该只有 1 个。
Also, you should assert the reset at time 0, wait for a delay, then deassert the reset.此外,您应该在时间 0 置位复位,等待延迟,然后取消置位复位。 This is another source of the unknowns.
这是未知数的另一个来源。 Since it is an active-low reset, set it to 0, then after a delay, set it to 1.
由于是低电平有效复位,将其设置为 0,然后在延迟后将其设置为 1。
This code gets rid of the unknown signals for me.这段代码为我摆脱了未知信号。
module seqgen();
wire q1,q2,q3,q4;
wire da;
reg clk = 1'b0, rstn = 0;
initial #25 rstn=1;
always #10 clk = ~clk;
assign da = ~q1|~q2|~q4;
DFF dffa(da,rstn,clk,q1);
DFF dffb(q1,rstn,clk,q2);
DFF dffc(q2,rstn,clk,q3);
DFF dffd(q3,rstn,clk,q4);
endmodule
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